1.1 --- a/AcornElectronMainboard.sch Sun Feb 27 17:46:10 2022 +0100
1.2 +++ b/AcornElectronMainboard.sch Sun Apr 03 18:39:26 2022 +0200
1.3 @@ -463,8 +463,6 @@
1.4 $EndSheet
1.5 Wire Bus Line
1.6 2100 2300 1700 2300
1.7 -Wire Bus Line
1.8 - 2100 1600 1700 1600
1.9 Text GLabel 1700 1600 0 50 BiDi ~ 0
1.10 RAM[0..3]
1.11 Text GLabel 1700 2300 0 50 Output ~ 0
1.12 @@ -985,6 +983,8 @@
1.13 Text Notes 4550 1400 0 50 ~ 0
1.14 Note that KiCad gets upset\nwhen connecting passives\nto power input pins.
1.15 Wire Bus Line
1.16 + 1700 1600 2100 1600
1.17 +Wire Bus Line
1.18 2100 1600 2100 1900
1.19 Wire Bus Line
1.20 2100 3100 2100 3400