1 The Am29F010-90PC product has been used to test the software and hardware
2 design described here.
3
4 Device Compatibility
5 ====================
6
7 For use with an Acorn Electron ROM cartridge or other board providing a ROM
8 socket, the compatibility of the Am29F010 needs to be assessed in the context
9 of the ROM sockets likely to be provided.
10
11 Original ROM Pinout Am29F010 Pinout
12 ------------------- ---------------
13
14 1 \/ 32 VCC
15 A16 2 31 WE#
16 1 \/ 28 VCC A15 3 30
17 A12 2 27 A14 A12 4 29 A14
18 A7 3 26 A13 A7 5 28 A13
19 A6 4 25 A8 A6 6 27 A8
20 A5 5 24 A9 A5 7 26 A9
21 A4 6 23 A11 A4 8 25 A11
22 A3 7 22 OE# A3 9 24 OE#
23 A2 8 21 A10 A2 10 23 A10
24 A1 9 20 CS# A1 11 22 CE#
25 A0 10 19 D7 A0 12 21 DQ7
26 D0 11 18 D6 DQ0 13 20 DQ6
27 D1 12 17 D5 DQ1 14 19 DQ5
28 D2 13 16 D4 DQ2 15 18 DQ4
29 GND 14 15 D3 GND/VSS 16 17 DQ3
30
31 Superimposing the Am29F010 onto a ROM socket would provide compatibility for
32 all pins from A12 to GND/VSS and from A14 to D3/DQ3.
33
34 Pin 1 in a ROM socket would correspond to A15 but is not necessarily
35 connected, nor, perhaps, is A14 since only 14 bits are required to address 16
36 kilobytes, although there may be 32 kilobyte sockets connecting A14 and using
37 15 bits to address 32K. A16 and A15 would probably be connected to ground to
38 ensure correct operation, but could also be wired to a selection mechanism so
39 that the entire contents of the flash memory might be exposed.
40
41 Pin 28 is a ROM socket would provide power, but the corresponding pin 30 on an
42 Am29F010 is not connected. Thus pin 30 would need routing to pin 32 for the
43 flash device socket.
44
45 Pin 31 for the Am29F010 would need to be asserted. Thus pin 30 might also be
46 routed to pin 31, so that the device would remain read-only at all times.
47
48 Dual ROM Adapter Usage
49 ======================
50
51 A single Am29F010 device could be wired to two ROM sockets in order to provide
52 data to both. The above wiring guide would be employed, with connections from
53 both sockets being connected to the Am29F010, but additional logic would be
54 required for the CS# signals originating from the sockets in order to expose
55 the appropriate region of flash memory. ROM #1 would be served by a "lower"
56 16K region; ROM #2 would be served by an "upper" 16K region; A14 would be used
57 to switch between these regions.
58
59 When ROM #1's CS# signal is low, an attempt to read from ROM #1 would be
60 occurring, and thus A14 would be held low. And when ROM #2's CS# signal is
61 low, an attempt to read from ROM #2 would be occurring, and thus A14 would be
62 held high.
63
64 ROM #1 CS# ROM #2 CS# Am29F010 A14
65 ---------- ---------- ------------
66 0 0 Not defined
67 0 1 0
68 1 0 1
69 1 1 Not defined
70
71 It might therefore be possible to connect A14 to ROM #1's CS# signal.
72
73 Pins
74 ====
75
76 A0-A16 17-bit addressing
77 DQ0-DQ7 8-bit data transfer
78 CE# chip enable
79 OE# output enable
80 WE# write enable
81 VCC 5V
82 VSS ground
83 NC (not connected)
84
85 Low-Level Operations
86 ====================
87
88 CE# high standby
89 CE# low read, write or output disable
90
91 OE# high, WE# high output disable
92 OE# low, WE# high read
93 OE# high, WE# low write
94
95 Thus, for reading and writing:
96
97 OE# = not WE#
98
99 Timing
100 ======
101
102 Addresses are latched on the falling edge of the latest of WE# and CE#
103 Data is latched on the rising edge of the latest of WE# and CE#
104
105 Strategy:
106
107 1. Start with CE#, OE#, WE# high (standby, output disable)
108 2. Bring CE# low (output disable)
109 3. Set addresses
110 4. Bring WE# or OE# low for operation (write or read)
111 5. Read or write data
112 6. Bring WE# or OE# high (output disable)
113
114 Operation Modes
115 ===============
116
117 By default, the device is in read mode, meaning that merely bringing OE# low
118 will produce data for the asserted address.
119
120 To issue commands to change the mode involves write operations with specific
121 address and data arguments.
122
123 Sectors
124 =======
125
126 A[16...14] selects each 16KB sector and is referred to as the sector address
127 or SA in the documentation.
128
129 Commands
130 ========
131
132 Reset (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$F0)
133
134 Autoselect (manufacturer) (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$90);
135 (A=$X00; read)
136 => D=$01
137
138 Autoselect (device) (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$90);
139 (A=$X01; read)
140 => D=$20
141
142 Simple reset (A=$XXXX; D=$F0)
143
144 Sector erase (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$80);
145 (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=SA; D=$30)
146
147 Program (A=$5555; D=$AA); (A=$2AAA; D=$55); (A=$5555; D=$A0);
148 (A=PA; D=PD)
149
150 Progress
151 --------
152
153 Programming and erasure commands employ data pins as follows:
154
155 Programming Erasure
156 DQ7 On completion: DQ7-out On completion: 1
157 DQ6 During: toggling value During: toggling value
158 DQ5 On failure: 1 On failure: 1
159 DQ3 Sector erase begun: 1
160
161 A read operation is required to obtain these outputs, typically with the same
162 address used to initiate each operation.
163
164 Arduino Interfacing
165 ===================
166
167 Arduino can employ at most 14 digital pins, whereas the Am29F010B requires 17
168 address pins, 8 data pins, plus 3 control pins to be utilised.
169
170 One solution is to map the 3 control pins directly to the Arduino, then to
171 channel address and data via 8 common pins to latches, and then employ the
172 remaining pins to control the latches.
173
174 Two pins can be used to select the latches, and when neither latch is
175 selected, the data pins will be used to read or write data from the flash
176 memory.
177
178 As a result, only 13 pins are needed on the Arduino.
179
180 74HC273 Pinout
181 --------------
182
183 MR# 1 \/ 20 VCC
184 Q0 2 19 Q7
185 D0 3 18 D7
186 D1 4 17 D6
187 Q1 5 16 Q6
188 Q2 6 15 Q5
189 D2 7 14 D5
190 D3 8 13 D4
191 Q3 9 12 Q4
192 GND 10 11 CP
193
194 Arduino 74HC273 #1 74HC273 #2 Am29F010
195 ------- ---------- ---------- --------
196 A5 CE#
197 A4 OE#
198 A3 WE#
199 2 CP
200 3 CP
201 4 D0 D0 DQ0
202 5 D1 D1 DQ1
203 6 D2 D2 DQ2
204 7 D3 D3 DQ3
205 8 D4 D4 DQ4
206 9 D5 D5 DQ5
207 10 D6 D6 DQ6
208 11 D7 D7 DQ7
209 Q0 A0
210 Q1 A1
211 Q2 A2
212 Q3 A3
213 Q4 A4
214 Q5 A5
215 Q6 A6
216 Q7 A7
217 Q0 A8
218 Q1 A9
219 Q2 A10
220 Q3 A11
221 Q4 A12
222 Q5 A13
223 Q6 A14
224 Q7 A15
225 GND A16 (not used)
226 5V MR# MR#
227 5V VCC VCC VCC
228 GND GND GND VSS
229
230 Set Address
231 -----------
232
233 74HC273 #1 CP = 1; 74HC273 #2 CP = 0
234 74HC273 #1 D[7...0] = A[7...0]
235 74HC273 #1 CP = 0; 74HC273 #2 CP = 1
236 74HC273 #2 D[7...0] = A[15...8]
237
238 Write Data
239 ----------
240
241 Configure pins as D[7...0]
242 WE# = 0
243 74HC273 #1 CP = 0; 74HC273 #2 CP = 0
244 74HC273 #3 D[7...0] = D[7...0]
245 WE# = 1
246
247 Read Data
248 ---------
249
250 Configure pins as Q[7...0]
251 OE# = 0
252 74HC273 #1 CP = 1; 74HC273 #2 CP = 0
253 Q[7...0] = 74HC273 #0 Q[7...0]
254 OE# = 1