1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/pic32.h Mon Oct 15 21:59:18 2018 +0200
1.3 @@ -0,0 +1,125 @@
1.4 +#ifndef __PIC32_H__
1.5 +#define __PIC32_H__
1.6 +
1.7 +/* See...
1.8 + * TABLE 4-1: SFR MEMORYMAP
1.9 + * TABLE 11-3: PORTA REGISTER MAP
1.10 + * 11.2 CLR, SET and INV Registers
1.11 + * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet
1.12 + */
1.13 +
1.14 +#define OC1CON 0xBF803000
1.15 +#define OC1R 0xBF803010
1.16 +#define OC1RS 0xBF803020
1.17 +#define OC2CON 0xBF803200
1.18 +#define OC2R 0xBF803210
1.19 +#define OC2RS 0xBF803220
1.20 +#define OC3CON 0xBF803400
1.21 +#define OC3R 0xBF803410
1.22 +#define OC3RS 0xBF803420
1.23 +
1.24 +#define T1CON 0xBF800600
1.25 +#define TMR1 0xBF800610
1.26 +#define PR1 0xBF800620
1.27 +#define T2CON 0xBF800800
1.28 +#define TMR2 0xBF800810
1.29 +#define PR2 0xBF800820
1.30 +#define T3CON 0xBF800A00
1.31 +#define TMR3 0xBF800A10
1.32 +#define PR3 0xBF800A20
1.33 +
1.34 +#define U1MODE 0xBF806000
1.35 +#define U1STA 0xBF806010
1.36 +#define U1TXREG 0xBF806020
1.37 +#define U1RXREG 0xBF806030
1.38 +#define U1BRG 0xBF806040
1.39 +
1.40 +#define PMCON 0xBF807000
1.41 +#define PMMODE 0xBF807010
1.42 +#define PMADDR 0xBF807020
1.43 +#define PMDOUT 0xBF807030
1.44 +#define PMDIN 0xBF807040
1.45 +#define PMAEN 0xBF807050
1.46 +#define PMSTAT 0xBF807060
1.47 +
1.48 +#define OSCCON 0xBF80F000
1.49 +#define REFOCON 0xBF80F020
1.50 +#define REFOTRIM 0xBF80F030
1.51 +#define CFGCON 0xBF80F200
1.52 +#define SYSKEY 0xBF80F230
1.53 +
1.54 +#define U1RXR 0xBF80FA50
1.55 +
1.56 +#define RPA0R 0xBF80FB00
1.57 +#define RPA1R 0xBF80FB04
1.58 +#define RPA2R 0xBF80FB08
1.59 +#define RPA3R 0xBF80FB0C
1.60 +#define RPA4R 0xBF80FB10
1.61 +#define RPB0R 0xBF80FB2C
1.62 +#define RPB1R 0xBF80FB30
1.63 +#define RPB2R 0xBF80FB34
1.64 +#define RPB3R 0xBF80FB38
1.65 +#define RPB4R 0xBF80FB3C
1.66 +#define RPB5R 0xBF80FB40
1.67 +#define RPB10R 0xBF80FB54
1.68 +#define RPB15R 0xBF80FB68
1.69 +
1.70 +#define INTCON 0xBF881000
1.71 +#define IFS0 0xBF881030
1.72 +#define IFS1 0xBF881040
1.73 +#define IEC0 0xBF881060
1.74 +#define IEC1 0xBF881070
1.75 +#define IPC1 0xBF8810A0
1.76 +#define IPC2 0xBF8810B0
1.77 +#define IPC7 0xBF881100
1.78 +#define IPC8 0xBF881110
1.79 +#define IPC10 0xBF881130
1.80 +
1.81 +#define BMXCON 0xBF882000
1.82 +#define BMXDKPBA 0xBF882010
1.83 +#define BMXDUDBA 0xBF882020
1.84 +#define BMXDUPBA 0xBF882030
1.85 +#define BMXDRMSZ 0xBF882040
1.86 +
1.87 +#define DMACON 0xBF883000
1.88 +#define DCH0CON 0xBF883060
1.89 +#define DCH0ECON 0xBF883070
1.90 +#define DCH0INT 0xBF883080
1.91 +#define DCH0SSA 0xBF883090
1.92 +#define DCH0DSA 0xBF8830A0
1.93 +#define DCH0SSIZ 0xBF8830B0
1.94 +#define DCH0DSIZ 0xBF8830C0
1.95 +#define DCH0CSIZ 0xBF8830F0
1.96 +#define DCH1CON 0xBF883120
1.97 +#define DCH1ECON 0xBF883130
1.98 +#define DCH1INT 0xBF883140
1.99 +#define DCH1SSA 0xBF883150
1.100 +#define DCH1DSA 0xBF883160
1.101 +#define DCH1SSIZ 0xBF883170
1.102 +#define DCH1DSIZ 0xBF883180
1.103 +#define DCH1CSIZ 0xBF8831B0
1.104 +#define DCH2CON 0xBF8831E0
1.105 +#define DCH2ECON 0xBF8831F0
1.106 +#define DCH2INT 0xBF883200
1.107 +#define DCH2SSA 0xBF883210
1.108 +#define DCH2DSA 0xBF883220
1.109 +#define DCH2SSIZ 0xBF883230
1.110 +#define DCH2DSIZ 0xBF883240
1.111 +#define DCH2CSIZ 0xBF883270
1.112 +
1.113 +#define ANSELA 0xBF886000
1.114 +#define TRISA 0xBF886010
1.115 +#define PORTA 0xBF886020
1.116 +#define LATA 0xBF886030
1.117 +#define ODCA 0xBF886040
1.118 +#define ANSELB 0xBF886100
1.119 +#define TRISB 0xBF886110
1.120 +#define PORTB 0xBF886120
1.121 +#define LATB 0xBF886130
1.122 +#define ODCB 0xBF886140
1.123 +
1.124 +#define CLR 0x4
1.125 +#define SET 0x8
1.126 +#define INV 0xC
1.127 +
1.128 +#endif /* __PIC32_H__ */