# HG changeset patch # User Paul Boddie # Date 1539633558 -7200 # Node ID 47e3885a4c3ad8bb7df1d9966f074342131c1cda A simple LED-blinking demonstration for MIPS-based PIC32 microcontrollers. diff -r 000000000000 -r 47e3885a4c3a Makefile --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Makefile Mon Oct 15 21:59:18 2018 +0200 @@ -0,0 +1,75 @@ +# Makefile - Build the BlinkPIC32 payload +# +# Copyright (C) 2015, 2017, 2018 Paul Boddie +# Copyright (C) Xiangfu Liu +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +ARCH = mipsel-linux-gnu +CC = $(ARCH)-gcc +LD = $(ARCH)-ld +NM = $(ARCH)-nm +OBJCOPY=$(ARCH)-objcopy +OBJDUMP=$(ARCH)-objdump + +# NOTE: -O2 is actually needed to prevent memcpy references, whereas probably +# NOTE: one of the -f{freestanding, no-hosted, no-builtin} options should work. +# NOTE: See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56888 + +CFLAGS = -O2 -Wall \ + -fno-unit-at-a-time -fno-zero-initialized-in-bss \ + -ffreestanding -fno-hosted -fno-builtin \ + -march=mips32 +LDFLAGS = -nostdlib -EL + +TARGET = blink.elf +DUMP = $(TARGET:.elf=.dump) +MAP = $(TARGET:.elf=.map) +SCRIPT = $(TARGET:.elf=.ld) + +HEX = $(TARGET:.elf=.hex) +SREC = $(TARGET:.elf=.srec) + +# Ordering of objects is important and cannot be left to replacement rules. + +SRC = blink.S +OBJ = blink.o + +.PHONY: all clean distclean + +all: $(HEX) $(SREC) + +clean: + rm -f $(OBJ) $(TARGET) $(HEX) $(SREC) $(DUMP) *.map + +distclean: clean + echo "Nothing else to clean." + +$(HEX): $(TARGET) + $(OBJCOPY) -O ihex $(TARGET) $(HEX) + +$(SREC): $(TARGET) + $(OBJCOPY) -O srec $(TARGET) $(SREC) + +$(TARGET): $(OBJ) + $(LD) $(LDFLAGS) -T $(SCRIPT) $(OBJ) -o $@ + $(OBJDUMP) -D $(TARGET) > $(DUMP) + $(OBJDUMP) -h $(TARGET) > $(MAP) + $(NM) -n $(TARGET) > System.map + +.c.o: + $(CC) -c $(CFLAGS) $< -o $@ + +.S.o: + $(CC) -c $(CFLAGS) $< -o $@ diff -r 000000000000 -r 47e3885a4c3a README.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/README.txt Mon Oct 15 21:59:18 2018 +0200 @@ -0,0 +1,154 @@ +Introduction +------------ + +The BlinkPIC32 project provides software and circuit information to +demonstrate a trivial LED-blinking application using a PIC32 microcontroller, +in particular one with a DIP-28 profile that can be set up on a breadboard. + +Contact, Copyright and Licence Information +------------------------------------------ + +The author can be contacted at the following e-mail address: + +paul@boddie.org.uk + +Copyright and licence information can be found in the docs directory - see +docs/COPYING.txt and docs/gpl-3.0.txt for more information. + + + +Using the Software +================== + +The software to be transferred to the microcontroller can be built as follows: + +make + +This should produce a file called blink.hex that can then be transferred to the +device. This will toggle an output that can be connected to a light-emitting +diode (LED) to demonstrate the operation of the program. + + + +Hardware Details +================ + +The following pinout provides a summary of the pertinent functions associated +with the pins on the microcontroller. + +PIC32MX270F256B-50I/SP Pinout +----------------------------- + + 5 MCLR# 1 \/ 28 AVDD + cap RA0 2 27 AVSS + cap RA1 3 26 RB15 ap + cap PGED1/RB0 4 25 RB14 a + cap PGEC1/RB1 5 24 RB13 ap + cap RB2 6 23 VUSB3V3 + cap RB3 7 22 RB11/PGEC2 + VSS 8 21 RB10/PGED2 + c RA2 9 20 VCAP + cp RA3 10 19 VSS + c RB4 11 18 RB9/TDO 5cp + cp RA4 12 17 RB8/TCK 5cp + VDD 13 16 RB7/TDI 5cp + 5c TMS/RB5 14 15 VBUS 5 + + default pin supply limitation of -0.3V to VDD + 0.3V +5 = 5V-tolerant pin with supply limitation of -0.3V to 5.5V if VDD >= 2.3V +a = analogue/digital pin +c = permit change notification configuration +p = parallel master/slave port pin + +Thus, there should be up to 5 5V-tolerant I/O pins. + +The microcontroller can be set up to function normally in a breadboard circuit +and also be connected up to a programming circuit at the same time. This +permits immediate feedback about the programming of the device without the +need to connect and disconnect the programmer. + + + +Breadboard Circuit +================== + +In order to be programmed and to function normally, the device needs to be +deployed in a circuit configured as follows: + +PIC32MX270F256B-50I/SP +---------------------- +MCLR# 3.3V (via 10K pull-up resistor) +VSS GND +VDD 3.3V +VSS GND +VCAP GND (via 10µF capacitor) +VUSB3V3 3.3V +AVSS GND +AVDD 3.3V + +"Figure 2-1: Recommended Minimum Connection" from the "PIC32MX1XX/2XX +28/36/44-pin Family Data Sheet" stipulates additional 0.1µF ceramic capacitors +between VDD and VSS and between AVDD and AVSS. + + + +Demonstration Circuit +===================== + +To test the software payload, the RA3 pin should be connected to a LED in +series with a 100 ohm resistor, routing to GND. + +PIC32MX270F256B-50I/SP +---------------------- +RA3 LED -> GND (via 100 ohm resistor) + + + +ICSP Programming Circuit +======================== + +To avoid limitations with JTAG programming and associated limitations it may +impose on pin usage, the ICSP mechanism needs to be employed instead. The +circuit should resemble the following: + +PIC32MX270F256B-50I/SP Arduino +---------------------- ------- +MCLR# A0 +PGEC1/PGEC2 A2 (pulled up via 2K2 resistor to 3.3V) +PGED1/PGED2 A1 (via 220ohm resistor, then pulled up via 2K2 + resistor to 3.3V) + +The pull-up from MCLR# to VDD can apparently be left in place. + +The Pickle and Nanu Nanu software are used for programming: + +https://wiki.kewl.org/dokuwiki/projects:pickle +https://wiki.kewl.org/dokuwiki/projects:nanu-nanu + +Nanu Nanu can be deployed in the 5V-16M configuration on an Arduino +Duemilanove with an "open drain" or "sink" circuit as described above. Then, +the pload program provided by Pickle can be used to write the boot.hex file as +follows (as a sufficiently privileged user): + +./pload program /dev/ttyUSB0 blink.hex + +Note that the Pickle configuration file (~/.pickle or ~/.pickle/config) will +need to have the port and baudrate settings defined. For example: + +DEVICE=/dev/ttyUSB0 +BAUDRATE=115200 +DEBUG=1 + + + +References +========== + +Basic PIC32 breadboard circuit: + +http://umassamherstm5.org/tech-tutorials/pic32-tutorials/pic32mx220-tutorials/pic32mx220-breadboard + +ArduPIC32 JTAG-based programmer: + +http://www.microchip.com/forums/m653443.aspx +https://code.google.com/archive/p/ardupic32/ diff -r 000000000000 -r 47e3885a4c3a blink.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/blink.S Mon Oct 15 21:59:18 2018 +0200 @@ -0,0 +1,116 @@ +/* + * Blink LEDs using a PIC32 microcontroller. + * + * Copyright (C) 2017, 2018 Paul Boddie + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "mips.h" +#include "pic32.h" + +/* Disable JTAG functionality on pins. */ + +.section .devcfg0, "a" +.word 0xfffffffb /* DEVCFG0<2> = JTAGEN = 0 */ + +/* +Set the oscillator to be the FRC oscillator with PLL, with peripheral clock +divided by 2, and FRCDIV+PLL selected. + +The watchdog timer (FWDTEN) is also disabled. + +The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with +RPB4. +*/ + +.section .devcfg1, "a" +.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1; + DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */ + +/* +Set the FRC oscillator PLL function with an input division of 4, an output +division of 2, a multiplication of 24, yielding a multiplication of 3. + +The FRC is apparently at 16MHz and this produces a system clock of 48MHz. +*/ + +.section .devcfg2, "a" +.word 0xfff9fffb /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001; + DEVCFG2<6:4> = FPLLMUL<2:0> = 111; + DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */ + +.text +.globl _start + +_start: + /* Set pins for output. */ + + jal init_pins + nop + + /* Clear output (LED). */ + + la $t0, PORTA + li $t1, (1 << 3) /* PORTA<3> = RA3 */ + sw $t1, CLR($t0) + + /* Main program. */ +main: + li $a1, (3 << 24) /* counter ~= 50000000 */ + + /* Monitoring loop. */ +loop: + addiu $a1, $a1, -1 /* counter -= 1 */ + bnez $a1, loop + nop + + /* Invert output (LED). */ + + la $t0, PORTA + li $t1, (1 << 3) /* PORTA<3> = RA3 */ + sw $t1, INV($t0) + + j main + nop + + + +init_pins: + /* DEVCFG0<2> needs setting to 0 before the program is run. */ + + la $v0, CFGCON + li $v1, (1 << 3) /* CFGCON<3> = JTAGEN = 0 */ + sw $v1, CLR($v0) + +init_outputs: + /* Remove analogue features from pins. */ + + la $v0, ANSELA + sw $zero, 0($v0) /* ANSELA = 0 */ + la $v0, ANSELB + sw $zero, 0($v0) /* ANSELB = 0 */ + + la $v0, TRISA + sw $zero, 0($v0) + la $v0, TRISB + sw $zero, 0($v0) + + la $v0, PORTA + sw $zero, 0($v0) + la $v0, PORTB + sw $zero, 0($v0) + + jr $ra + nop diff -r 000000000000 -r 47e3885a4c3a blink.ld --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/blink.ld Mon Oct 15 21:59:18 2018 +0200 @@ -0,0 +1,47 @@ +OUTPUT_ARCH(mips) +ENTRY(_start) + +/* See... + * FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX170/270 DEVICES (64 KB RAM, 256 KB FLASH) + * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet + */ + +MEMORY +{ + kseg1_data_mem (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x10000 + kseg0_boot_mem (rx) : ORIGIN = 0x9FC00000, LENGTH = 0xBF0 + kseg0_program_mem (rx) : ORIGIN = 0x9D000000, LENGTH = 0x40000 + physical_boot_mem (rx) : ORIGIN = 0x1FC00000, LENGTH = 0xBF0 + physical_program_mem (rx) : ORIGIN = 0x1D000000, LENGTH = 0x40000 + sfrs : ORIGIN = 0xBF800000, LENGTH = 0x100000 + configsfrs : ORIGIN = 0xBFC00BF0, LENGTH = 0x10 + config3 : ORIGIN = 0xBFC00BF0, LENGTH = 0x4 + config2 : ORIGIN = 0xBFC00BF4, LENGTH = 0x4 + config1 : ORIGIN = 0xBFC00BF8, LENGTH = 0x4 + config0 : ORIGIN = 0xBFC00BFC, LENGTH = 0x4 + physical_config3 : ORIGIN = 0x3FC00BF0, LENGTH = 0x4 + physical_config2 : ORIGIN = 0x3FC00BF4, LENGTH = 0x4 + physical_config1 : ORIGIN = 0x3FC00BF8, LENGTH = 0x4 + physical_config0 : ORIGIN = 0x3FC00BFC, LENGTH = 0x4 +} + +SECTIONS +{ + .text : { *(.text*) } > kseg0_boot_mem AT > physical_boot_mem + .flash : { *(.flash*) } > kseg0_program_mem AT > physical_program_mem + .bss : { *(.bss*) } > kseg1_data_mem + .got : { + _gp = ALIGN(16); + *(.got*) + } > kseg0_boot_mem AT > physical_boot_mem + .devcfg0 : { + *(.devcfg0) + } > config0 AT > physical_config0 + .devcfg1 : { + *(.devcfg1) + } > config1 AT > physical_config1 + .devcfg2 : { + *(.devcfg2) + } > config2 AT > physical_config2 + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } +} diff -r 000000000000 -r 47e3885a4c3a docs/COPYING.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/docs/COPYING.txt Mon Oct 15 21:59:18 2018 +0200 @@ -0,0 +1,19 @@ +Licence Agreement for BlinkPIC32 +-------------------------------- + +Original materials for this project: + +Copyright (C) 2017, 2018 Paul Boddie + +This program is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free Software +Foundation; either version 3 of the License, or (at your option) any later +version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +this program. If not, see . diff -r 000000000000 -r 47e3885a4c3a docs/gpl-3.0.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/docs/gpl-3.0.txt Mon Oct 15 21:59:18 2018 +0200 @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff -r 000000000000 -r 47e3885a4c3a mips.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mips.h Mon Oct 15 21:59:18 2018 +0200 @@ -0,0 +1,63 @@ +#ifndef __MIPS_H__ +#define __MIPS_H__ + +#define KSEG0_BASE 0x80000000 +#define KSEG1_BASE 0xA0000000 + +#define CP0_INDEX $0 +#define CP0_ENTRYLO0 $2 +#define CP0_ENTRYLO1 $3 +#define CP0_CONTEXT $4 +#define CP0_PAGEMASK $5 +#define CP0_WIRED $6 +#define CP0_BADVADDR $8 +#define CP0_COUNT $9 +#define CP0_ENTRYHI $10 +#define CP0_COMPARE $11 +#define CP0_STATUS $12 +#define CP0_INTCTL $12, 1 +#define CP0_CAUSE $13 +#define CP0_EPC $14 +#define CP0_EBASE $15, 1 +#define CP0_CONFIG $16 +#define CP0_WATCHLO $18 +#define CP0_DEBUG $23 +#define CP0_TAGLO $28 +#define CP0_TAGHI $29 +#define CP0_ERROREPC $30, 0 + +#define STATUS_CP0 0x10000000 +#define STATUS_BEV 0x00400000 + +#define STATUS_IRQ 0x0000fc00 +#define STATUS_IRQ_SHIFT 10 + +#define STATUS_UM 0x00000010 +#define STATUS_ERL 0x00000004 +#define STATUS_EXL 0x00000002 +#define STATUS_IE 0x00000001 + +#define CAUSE_IV 0x00800000 + +#define EBASE_MASK 0x3ffff000 + +#define INTCTL_MASK 0x000003e0 + +#define DEBUG_DM 0x40000000 + +#define TLB_CACHED 0x00000018 +#define TLB_UNCACHED 0x00000010 +#define TLB_DIRTY 0x00000004 +#define TLB_VALID 0x00000002 +#define TLB_GLOBAL 0x00000001 + +#define TLB_READ (TLB_CACHED | TLB_VALID) +#define TLB_WRITE (TLB_CACHED | TLB_DIRTY | TLB_VALID) +#define TLB_ALL_READ (TLB_CACHED | TLB_VALID | TLB_GLOBAL) +#define TLB_ALL_WRITE (TLB_CACHED | TLB_DIRTY | TLB_VALID | TLB_GLOBAL) + +#define CONFIG_K0 0x00000007 +#define CONFIG_K0_UNCACHED 2 +#define CONFIG_K0_CACHABLE_NONCOHERENT 3 + +#endif /* __MIPS_H__ */ diff -r 000000000000 -r 47e3885a4c3a pic32.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/pic32.h Mon Oct 15 21:59:18 2018 +0200 @@ -0,0 +1,125 @@ +#ifndef __PIC32_H__ +#define __PIC32_H__ + +/* See... + * TABLE 4-1: SFR MEMORYMAP + * TABLE 11-3: PORTA REGISTER MAP + * 11.2 CLR, SET and INV Registers + * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet + */ + +#define OC1CON 0xBF803000 +#define OC1R 0xBF803010 +#define OC1RS 0xBF803020 +#define OC2CON 0xBF803200 +#define OC2R 0xBF803210 +#define OC2RS 0xBF803220 +#define OC3CON 0xBF803400 +#define OC3R 0xBF803410 +#define OC3RS 0xBF803420 + +#define T1CON 0xBF800600 +#define TMR1 0xBF800610 +#define PR1 0xBF800620 +#define T2CON 0xBF800800 +#define TMR2 0xBF800810 +#define PR2 0xBF800820 +#define T3CON 0xBF800A00 +#define TMR3 0xBF800A10 +#define PR3 0xBF800A20 + +#define U1MODE 0xBF806000 +#define U1STA 0xBF806010 +#define U1TXREG 0xBF806020 +#define U1RXREG 0xBF806030 +#define U1BRG 0xBF806040 + +#define PMCON 0xBF807000 +#define PMMODE 0xBF807010 +#define PMADDR 0xBF807020 +#define PMDOUT 0xBF807030 +#define PMDIN 0xBF807040 +#define PMAEN 0xBF807050 +#define PMSTAT 0xBF807060 + +#define OSCCON 0xBF80F000 +#define REFOCON 0xBF80F020 +#define REFOTRIM 0xBF80F030 +#define CFGCON 0xBF80F200 +#define SYSKEY 0xBF80F230 + +#define U1RXR 0xBF80FA50 + +#define RPA0R 0xBF80FB00 +#define RPA1R 0xBF80FB04 +#define RPA2R 0xBF80FB08 +#define RPA3R 0xBF80FB0C +#define RPA4R 0xBF80FB10 +#define RPB0R 0xBF80FB2C +#define RPB1R 0xBF80FB30 +#define RPB2R 0xBF80FB34 +#define RPB3R 0xBF80FB38 +#define RPB4R 0xBF80FB3C +#define RPB5R 0xBF80FB40 +#define RPB10R 0xBF80FB54 +#define RPB15R 0xBF80FB68 + +#define INTCON 0xBF881000 +#define IFS0 0xBF881030 +#define IFS1 0xBF881040 +#define IEC0 0xBF881060 +#define IEC1 0xBF881070 +#define IPC1 0xBF8810A0 +#define IPC2 0xBF8810B0 +#define IPC7 0xBF881100 +#define IPC8 0xBF881110 +#define IPC10 0xBF881130 + +#define BMXCON 0xBF882000 +#define BMXDKPBA 0xBF882010 +#define BMXDUDBA 0xBF882020 +#define BMXDUPBA 0xBF882030 +#define BMXDRMSZ 0xBF882040 + +#define DMACON 0xBF883000 +#define DCH0CON 0xBF883060 +#define DCH0ECON 0xBF883070 +#define DCH0INT 0xBF883080 +#define DCH0SSA 0xBF883090 +#define DCH0DSA 0xBF8830A0 +#define DCH0SSIZ 0xBF8830B0 +#define DCH0DSIZ 0xBF8830C0 +#define DCH0CSIZ 0xBF8830F0 +#define DCH1CON 0xBF883120 +#define DCH1ECON 0xBF883130 +#define DCH1INT 0xBF883140 +#define DCH1SSA 0xBF883150 +#define DCH1DSA 0xBF883160 +#define DCH1SSIZ 0xBF883170 +#define DCH1DSIZ 0xBF883180 +#define DCH1CSIZ 0xBF8831B0 +#define DCH2CON 0xBF8831E0 +#define DCH2ECON 0xBF8831F0 +#define DCH2INT 0xBF883200 +#define DCH2SSA 0xBF883210 +#define DCH2DSA 0xBF883220 +#define DCH2SSIZ 0xBF883230 +#define DCH2DSIZ 0xBF883240 +#define DCH2CSIZ 0xBF883270 + +#define ANSELA 0xBF886000 +#define TRISA 0xBF886010 +#define PORTA 0xBF886020 +#define LATA 0xBF886030 +#define ODCA 0xBF886040 +#define ANSELB 0xBF886100 +#define TRISB 0xBF886110 +#define PORTB 0xBF886120 +#define LATB 0xBF886130 +#define ODCB 0xBF886140 + +#define CLR 0x4 +#define SET 0x8 +#define INV 0xC + +#endif /* __PIC32_H__ */