paul@15 | 1 | /* |
paul@15 | 2 | * PIC32 peripheral descriptions. |
paul@15 | 3 | * |
paul@15 | 4 | * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> |
paul@15 | 5 | * |
paul@15 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@15 | 7 | * it under the terms of the GNU General Public License as published by |
paul@15 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@15 | 9 | * (at your option) any later version. |
paul@15 | 10 | * |
paul@15 | 11 | * This program is distributed in the hope that it will be useful, |
paul@15 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@15 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@15 | 14 | * GNU General Public License for more details. |
paul@15 | 15 | * |
paul@15 | 16 | * You should have received a copy of the GNU General Public License |
paul@15 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@15 | 18 | */ |
paul@15 | 19 | |
paul@0 | 20 | #ifndef __PIC32_H__ |
paul@0 | 21 | #define __PIC32_H__ |
paul@0 | 22 | |
paul@3 | 23 | /* Peripheral addresses. |
paul@3 | 24 | * See... |
paul@0 | 25 | * TABLE 4-1: SFR MEMORYMAP |
paul@0 | 26 | * TABLE 11-3: PORTA REGISTER MAP |
paul@0 | 27 | * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet |
paul@0 | 28 | */ |
paul@0 | 29 | |
paul@0 | 30 | #define PMCON 0xBF807000 |
paul@0 | 31 | #define PMMODE 0xBF807010 |
paul@0 | 32 | #define PMADDR 0xBF807020 |
paul@0 | 33 | #define PMDOUT 0xBF807030 |
paul@0 | 34 | #define PMDIN 0xBF807040 |
paul@0 | 35 | #define PMAEN 0xBF807050 |
paul@0 | 36 | #define PMSTAT 0xBF807060 |
paul@0 | 37 | |
paul@0 | 38 | #define OSCCON 0xBF80F000 |
paul@0 | 39 | #define REFOCON 0xBF80F020 |
paul@0 | 40 | #define REFOTRIM 0xBF80F030 |
paul@0 | 41 | #define CFGCON 0xBF80F200 |
paul@0 | 42 | #define SYSKEY 0xBF80F230 |
paul@0 | 43 | |
paul@0 | 44 | #define U1RXR 0xBF80FA50 |
paul@0 | 45 | |
paul@0 | 46 | #define RPA0R 0xBF80FB00 |
paul@0 | 47 | #define RPA1R 0xBF80FB04 |
paul@0 | 48 | #define RPA2R 0xBF80FB08 |
paul@0 | 49 | #define RPA3R 0xBF80FB0C |
paul@0 | 50 | #define RPA4R 0xBF80FB10 |
paul@0 | 51 | #define RPB0R 0xBF80FB2C |
paul@0 | 52 | #define RPB1R 0xBF80FB30 |
paul@0 | 53 | #define RPB2R 0xBF80FB34 |
paul@0 | 54 | #define RPB3R 0xBF80FB38 |
paul@0 | 55 | #define RPB4R 0xBF80FB3C |
paul@0 | 56 | #define RPB5R 0xBF80FB40 |
paul@0 | 57 | #define RPB10R 0xBF80FB54 |
paul@0 | 58 | #define RPB15R 0xBF80FB68 |
paul@0 | 59 | |
paul@0 | 60 | #define INTCON 0xBF881000 |
paul@0 | 61 | #define IFS0 0xBF881030 |
paul@0 | 62 | #define IFS1 0xBF881040 |
paul@0 | 63 | #define IEC0 0xBF881060 |
paul@0 | 64 | #define IEC1 0xBF881070 |
paul@0 | 65 | #define IPC1 0xBF8810A0 |
paul@0 | 66 | #define IPC2 0xBF8810B0 |
paul@3 | 67 | #define IPC3 0xBF8810C0 |
paul@3 | 68 | #define IPC4 0xBF8810D0 |
paul@3 | 69 | #define IPC5 0xBF8810E0 |
paul@3 | 70 | #define IPC6 0xBF8810F0 |
paul@0 | 71 | #define IPC7 0xBF881100 |
paul@0 | 72 | #define IPC8 0xBF881110 |
paul@3 | 73 | #define IPC9 0xBF881120 |
paul@0 | 74 | #define IPC10 0xBF881130 |
paul@0 | 75 | |
paul@0 | 76 | #define BMXCON 0xBF882000 |
paul@0 | 77 | #define BMXDKPBA 0xBF882010 |
paul@0 | 78 | #define BMXDUDBA 0xBF882020 |
paul@0 | 79 | #define BMXDUPBA 0xBF882030 |
paul@0 | 80 | #define BMXDRMSZ 0xBF882040 |
paul@0 | 81 | |
paul@0 | 82 | #define ANSELA 0xBF886000 |
paul@0 | 83 | #define TRISA 0xBF886010 |
paul@0 | 84 | #define PORTA 0xBF886020 |
paul@0 | 85 | #define LATA 0xBF886030 |
paul@0 | 86 | #define ODCA 0xBF886040 |
paul@0 | 87 | #define ANSELB 0xBF886100 |
paul@0 | 88 | #define TRISB 0xBF886110 |
paul@0 | 89 | #define PORTB 0xBF886120 |
paul@0 | 90 | #define LATB 0xBF886130 |
paul@0 | 91 | #define ODCB 0xBF886140 |
paul@0 | 92 | |
paul@3 | 93 | /* DMA conveniences. */ |
paul@3 | 94 | |
paul@3 | 95 | #define DMACON 0xBF883000 |
paul@3 | 96 | #define DCH0CON 0xBF883060 |
paul@3 | 97 | #define DCH1CON 0xBF883120 |
paul@3 | 98 | #define DCH2CON 0xBF8831E0 |
paul@3 | 99 | #define DCH3CON 0xBF8832A0 |
paul@3 | 100 | |
paul@3 | 101 | #define DCHMIN 0 |
paul@3 | 102 | #define DCHMAX 3 |
paul@3 | 103 | #define DCHBASE DCH0CON |
paul@3 | 104 | #define DCHSTEP (DCH1CON - DCH0CON) |
paul@3 | 105 | |
paul@3 | 106 | #define DCHxCON 0x00 |
paul@3 | 107 | #define DCHxECON 0x10 |
paul@3 | 108 | #define DCHxINT 0x20 |
paul@3 | 109 | #define DCHxSSA 0x30 |
paul@3 | 110 | #define DCHxDSA 0x40 |
paul@3 | 111 | #define DCHxSSIZ 0x50 |
paul@9 | 112 | #define DCHxDSIZ 0x60 |
paul@9 | 113 | #define DCHxSPTR 0x70 |
paul@9 | 114 | #define DCHxDPTR 0x80 |
paul@3 | 115 | #define DCHxCSIZ 0x90 |
paul@9 | 116 | #define DCHxCPTR 0xA0 |
paul@9 | 117 | #define DCHxDAT 0xB0 |
paul@3 | 118 | |
paul@3 | 119 | #define DMAIEC IEC1 |
paul@3 | 120 | #define DMAIFS IFS1 |
paul@3 | 121 | #define DMAINTBASE 28 |
paul@14 | 122 | |
paul@3 | 123 | #define DMAIPC IPC10 |
paul@3 | 124 | #define DCHIPCBASE 0 |
paul@3 | 125 | #define DCHIPCSTEP 8 |
paul@3 | 126 | |
paul@14 | 127 | /* Output compare conveniences. */ |
paul@14 | 128 | |
paul@14 | 129 | #define OC1CON 0xBF803000 |
paul@14 | 130 | #define OC2CON 0xBF803200 |
paul@14 | 131 | #define OC3CON 0xBF803400 |
paul@14 | 132 | #define OC4CON 0xBF803600 |
paul@14 | 133 | #define OC5CON 0xBF803800 |
paul@14 | 134 | |
paul@14 | 135 | #define OCMIN 1 |
paul@14 | 136 | #define OCMAX 5 |
paul@14 | 137 | #define OCBASE OC1CON |
paul@14 | 138 | #define OCSTEP (OC2CON - OC1CON) |
paul@14 | 139 | |
paul@14 | 140 | #define OCxCON 0x00 |
paul@14 | 141 | #define OCxR 0x10 |
paul@14 | 142 | #define OCxRS 0x20 |
paul@14 | 143 | |
paul@14 | 144 | #define OCIEC IEC0 |
paul@14 | 145 | |
paul@14 | 146 | #define OCxIE 1 |
paul@14 | 147 | |
paul@14 | 148 | #define OCIFS IFS0 |
paul@14 | 149 | |
paul@14 | 150 | #define OCxIF 1 |
paul@14 | 151 | |
paul@14 | 152 | #define OCINTBASE 7 |
paul@14 | 153 | #define OCINTSTEP 5 |
paul@14 | 154 | |
paul@14 | 155 | #define OC1IPC IPC1 |
paul@14 | 156 | #define OC2IPC IPC2 |
paul@14 | 157 | #define OC3IPC IPC3 |
paul@14 | 158 | #define OC4IPC IPC4 |
paul@14 | 159 | #define OC5IPC IPC5 |
paul@14 | 160 | #define OCIPCBASE 16 |
paul@14 | 161 | |
paul@7 | 162 | /* Timer conveniences. */ |
paul@7 | 163 | |
paul@7 | 164 | #define T1CON 0xBF800600 |
paul@7 | 165 | #define T2CON 0xBF800800 |
paul@7 | 166 | #define T3CON 0xBF800A00 |
paul@7 | 167 | #define T4CON 0xBF800C00 |
paul@7 | 168 | #define T5CON 0xBF800E00 |
paul@7 | 169 | |
paul@7 | 170 | #define TIMERMIN 1 |
paul@7 | 171 | #define TIMERMAX 5 |
paul@7 | 172 | #define TIMERBASE T1CON |
paul@7 | 173 | #define TIMERSTEP (T2CON - T1CON) |
paul@7 | 174 | |
paul@7 | 175 | #define TxCON 0x00 |
paul@7 | 176 | #define TMRx 0x10 |
paul@7 | 177 | #define PRx 0x20 |
paul@7 | 178 | |
paul@7 | 179 | #define TIMERIEC IEC0 |
paul@7 | 180 | |
paul@7 | 181 | #define TxIE 1 |
paul@7 | 182 | |
paul@7 | 183 | #define TIMERIFS IEC0 |
paul@7 | 184 | |
paul@7 | 185 | #define TxIF 1 |
paul@7 | 186 | |
paul@7 | 187 | #define TIMERINTBASE 4 |
paul@7 | 188 | #define TIMERINTSTEP 5 |
paul@7 | 189 | |
paul@7 | 190 | #define TIMER1IPC IPC1 |
paul@7 | 191 | #define TIMER2IPC IPC2 |
paul@7 | 192 | #define TIMER3IPC IPC3 |
paul@7 | 193 | #define TIMER4IPC IPC4 |
paul@7 | 194 | #define TIMER5IPC IPC5 |
paul@7 | 195 | #define TIMERIPCBASE 0 |
paul@7 | 196 | |
paul@3 | 197 | /* UART conveniences. */ |
paul@3 | 198 | |
paul@3 | 199 | #define U1MODE 0xBF806000 |
paul@3 | 200 | #define U2MODE 0xBF806200 |
paul@3 | 201 | |
paul@3 | 202 | #define UARTMIN 1 |
paul@3 | 203 | #define UARTMAX 2 |
paul@3 | 204 | #define UARTBASE U1MODE |
paul@3 | 205 | #define UARTSTEP (U2MODE - U1MODE) |
paul@3 | 206 | |
paul@3 | 207 | #define UxMODE 0x00 |
paul@3 | 208 | #define UxSTA 0x10 |
paul@3 | 209 | #define UxTXREG 0x20 |
paul@3 | 210 | #define UxRXREG 0x30 |
paul@3 | 211 | #define UxBRG 0x40 |
paul@3 | 212 | |
paul@3 | 213 | #define UARTIEC IEC1 |
paul@6 | 214 | |
paul@6 | 215 | #define UxEIE 1 |
paul@6 | 216 | #define UxRIE 2 |
paul@6 | 217 | #define UxTIE 4 |
paul@6 | 218 | |
paul@3 | 219 | #define UARTIFS IFS1 |
paul@6 | 220 | |
paul@6 | 221 | #define UxEIF 1 |
paul@6 | 222 | #define UxRIF 2 |
paul@6 | 223 | #define UxTIF 4 |
paul@6 | 224 | |
paul@3 | 225 | #define UARTINTBASE 7 |
paul@3 | 226 | #define UARTINTSTEP 14 |
paul@6 | 227 | |
paul@3 | 228 | #define UART1IPC IPC8 |
paul@3 | 229 | #define UART1IPCBASE 0 |
paul@3 | 230 | #define UART2IPC IPC9 |
paul@3 | 231 | #define UART2IPCBASE 8 |
paul@3 | 232 | |
paul@3 | 233 | /* Interrupt numbers. |
paul@3 | 234 | * See... |
paul@3 | 235 | * TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION |
paul@3 | 236 | * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet |
paul@3 | 237 | */ |
paul@3 | 238 | |
paul@9 | 239 | #define DMA0 60 |
paul@9 | 240 | #define DMA1 61 |
paul@9 | 241 | #define DMA2 62 |
paul@9 | 242 | #define DMA3 63 |
paul@14 | 243 | #define OC1 7 |
paul@14 | 244 | #define OC2 12 |
paul@14 | 245 | #define OC3 17 |
paul@14 | 246 | #define OC4 22 |
paul@14 | 247 | #define OC5 27 |
paul@7 | 248 | #define T1 4 |
paul@7 | 249 | #define T2 9 |
paul@7 | 250 | #define T3 14 |
paul@7 | 251 | #define T4 19 |
paul@7 | 252 | #define T5 24 |
paul@3 | 253 | #define U1RX 40 |
paul@9 | 254 | #define U1TX 41 |
paul@3 | 255 | #define U2RX 54 |
paul@9 | 256 | #define U2TX 55 |
paul@3 | 257 | |
paul@3 | 258 | /* Address modifiers. |
paul@3 | 259 | * See... |
paul@3 | 260 | * 11.2 CLR, SET and INV Registers |
paul@3 | 261 | * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet |
paul@3 | 262 | */ |
paul@3 | 263 | |
paul@3 | 264 | #define CLR 0x4 |
paul@3 | 265 | #define SET 0x8 |
paul@3 | 266 | #define INV 0xC |
paul@0 | 267 | |
paul@0 | 268 | #endif /* __PIC32_H__ */ |