paul@35 | 1 | Introduction
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paul@35 | 2 | ------------
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paul@35 | 3 |
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paul@35 | 4 | This example demonstrates the generation of an analogue VGA signal from a
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paul@35 | 5 | PIC32 microcontroller using the parallel mode (parallel master port, PMP)
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paul@35 | 6 | peripheral. The result is not entirely satisfactory:
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paul@35 | 7 |
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paul@35 | 8 | * Pixels are very narrow unless buffered using a flip-flop driven by the
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paul@35 | 9 | peripheral, this being a characteristic of the way the peripheral works, it
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paul@35 | 10 | normally being used to drive memory and display controllers.
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paul@35 | 11 |
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paul@35 | 12 | * Introducing a flip-flop means that the final pixel from the pixel data
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paul@35 | 13 | remains asserted and must be reset using a second DMA channel.
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paul@35 | 14 |
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paul@35 | 15 | * Every fourth pixel is wider than the others, this apparently being an
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paul@35 | 16 | artefact of the DMA transfer mechanism.
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paul@35 | 17 |
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paul@35 | 18 | It might be possible introduce some kind of delay to the write strobe (PMWR)
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paul@35 | 19 | and even out the pixel widths, but this has not been investigated.
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paul@35 | 20 |
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paul@35 | 21 | It appears to be the case that the system and peripheral clock frequencies
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paul@35 | 22 | need to be matched. In this example, a frequency of 48MHz has been chosen.
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paul@35 | 23 |
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paul@35 | 24 | Hardware Details
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paul@35 | 25 | ================
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paul@35 | 26 |
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paul@35 | 27 | The pin usage of this solution is documented below.
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paul@35 | 28 |
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paul@35 | 29 | PIC32MX270F256B-50I/SP Pin Assignments
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paul@35 | 30 | --------------------------------------
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paul@35 | 31 |
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paul@35 | 32 | MCLR# 1 \/ 28
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paul@35 | 33 | D7/PMD7/RA0 2 27
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paul@35 | 34 | D6/PMD6/RA1 3 26 RB15/U1TX
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paul@35 | 35 | D0/PMD0/RB0 4 25 RB14
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paul@35 | 36 | D1/PMD1/RB1 5 24 RB13/(PMRD)/U1RX
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paul@35 | 37 | D2/PMD2/RB2 6 23
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paul@35 | 38 | PMWR/RB3 7 22 RB11/PGEC2
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paul@35 | 39 | 8 21 RB10/PGEC3
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paul@35 | 40 | RA2 9 20
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paul@35 | 41 | (PMA0)/RA3 10 19
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paul@35 | 42 | HSYNC/OC1/RB4 11 18 RB9/PMD3/D3
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paul@35 | 43 | 12 17 RB8/PMD4/D4
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paul@35 | 44 | 13 16 RB7/PMD5/D5
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paul@35 | 45 | VSYNC/OC2/RB5 14 15
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paul@35 | 46 |
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paul@35 | 47 | Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
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paul@35 | 48 | unlike the MX170 variant).
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paul@35 | 49 |
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paul@35 | 50 | UART Connections
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paul@35 | 51 | ----------------
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paul@35 | 52 |
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paul@35 | 53 | UART1 is exposed by the RB13 and RB15 pins.
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paul@35 | 54 |
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paul@35 | 55 | Data Signal Routing
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paul@35 | 56 | -------------------
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paul@35 | 57 |
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paul@35 | 58 | A flip-flop is used to buffer the outputs:
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paul@35 | 59 |
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paul@35 | 60 | Dn -> 74HC273:Dn
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paul@35 | 61 | 74HC273:Qn -> Qn
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paul@35 | 62 | VCC -> 74HC273:MR#
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paul@35 | 63 | PMWR -> 74HC273:CP
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paul@35 | 64 |
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paul@35 | 65 | For two bits of intensity, two bits per colour channel:
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paul@35 | 66 |
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paul@35 | 67 | Q7 -> 2200R -> I
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paul@35 | 68 | Q6 -> 4700R -> I
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paul@35 | 69 |
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paul@35 | 70 | I -> diode -> R
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paul@35 | 71 | I -> diode -> G
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paul@35 | 72 | I -> diode -> B
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paul@35 | 73 |
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paul@35 | 74 | Q5 -> 470R -> R
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paul@35 | 75 | Q4 -> 1000R -> R
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paul@35 | 76 | Q3 -> 470R -> G
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paul@35 | 77 | Q2 -> 1000R -> G
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paul@35 | 78 | Q1 -> 470R -> B
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paul@35 | 79 | Q0 -> 1000R -> B
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paul@35 | 80 |
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paul@35 | 81 | HSYNC -> HS
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paul@35 | 82 | VSYNC -> VS
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paul@35 | 83 |
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paul@35 | 84 | Output Socket Pinout
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paul@35 | 85 | --------------------
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paul@35 | 86 |
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paul@35 | 87 | 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R)
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paul@35 | 88 |
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paul@35 | 89 | 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND)
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paul@35 | 90 |
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paul@35 | 91 | 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC)
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paul@35 | 92 |
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paul@35 | 93 | Output Cable Pinout
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paul@35 | 94 | -------------------
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paul@35 | 95 |
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paul@35 | 96 | 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND)
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paul@35 | 97 |
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paul@35 | 98 | 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND)
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paul@35 | 99 |
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paul@35 | 100 | 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC)
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paul@35 | 101 |
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paul@35 | 102 | References
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paul@35 | 103 | ----------
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paul@35 | 104 |
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paul@35 | 105 | https://en.wikipedia.org/wiki/VGA_connector
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paul@35 | 106 |
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paul@35 | 107 | http://papilio.cc/index.php?n=Papilio.VGAWing
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paul@35 | 108 |
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paul@35 | 109 | http://lucidscience.com/pro-vga%20video%20generator-2.aspx
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paul@35 | 110 |
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paul@35 | 111 | https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga
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