paul@37 | 1 | Introduction
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paul@37 | 2 | ------------
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paul@37 | 3 |
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paul@37 | 4 | This example demonstrates the generation of an analogue VGA signal from a
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paul@37 | 5 | PIC32 microcontroller using general output pins. Unlike the vga and vga-pmp
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paul@37 | 6 | examples, it employs a regular interrupt condition to schedule single-byte
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paul@37 | 7 | (single-pixel) DMA transfers instead of a single whole-line transfer.
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paul@37 | 8 |
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paul@37 | 9 | The principal advantage of this method over the whole-line transfer method is
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paul@37 | 10 | its production of pixels with consistent widths. The principal disadvantage is
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paul@37 | 11 | the significant loss of horizontal resolution due to the latencies involved in
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paul@37 | 12 | propagating interrupt conditions to the DMA controller and thereby initiating
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paul@37 | 13 | each transfer.
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paul@37 | 14 |
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paul@37 | 15 | Employing a peripheral clock that has half the frequency of the system clock
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paul@37 | 16 | should ensure the stability of the picture, since the lower frequency may make
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paul@37 | 17 | transfers easier to schedule. The peripheral clock should provide a more
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paul@37 | 18 | forgiving deadline for each transfer, permitting late transfers to complete on
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paul@37 | 19 | time.
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paul@37 | 20 |
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paul@37 | 21 | Meanwhile, matching the system and peripheral clock frequencies appears to
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paul@37 | 22 | leave the scheduling of transfers open to uncertainty, with transfers being
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paul@37 | 23 | more readily delayed by other activity in the system, and with instability of
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paul@37 | 24 | the picture being the result.
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paul@37 | 25 |
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paul@37 | 26 | In contrast to the vga and vga-pmp examples, a special DMA channel is employed
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paul@37 | 27 | to initiate the pixel transfer process without actually transferring any pixel
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paul@37 | 28 | data itself. The channel arrangement is as follows:
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paul@37 | 29 |
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paul@37 | 30 | Transfer Initiator DMA Channel Transfer Activity
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paul@37 | 31 | ------------------ ----------- -----------------
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paul@37 | 32 | Timer2 DMA0 zerodata -> PORTB
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paul@37 | 33 | Timer3 DMA1 linedata -> PORTB
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paul@37 | 34 | DMA1 (completion) DMA2 zerodata -> PORTB
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paul@37 | 35 |
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paul@37 | 36 | The real purpose of this channel (DMA0) is to capture the Timer2 interrupt
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paul@37 | 37 | condition and to enable the following channel (DMA1) through channel chaining.
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paul@37 | 38 | Having been enabled, DMA1 is then able to conduct transfers at a tempo
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paul@37 | 39 | dictated by Timer3. Finally, DMA2 acts as the "reset" or "zero" channel to
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paul@37 | 40 | ensure that the pixel level is set to black at the end of each display line.
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paul@37 | 41 |
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paul@37 | 42 | In principle, other initiating conditions can be used instead of Timer3, which
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paul@37 | 43 | is configured to produce such conditions as frequently as possible:
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paul@37 | 44 |
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paul@37 | 45 | * A persistent interrupt condition can be employed instead. For example,
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paul@37 | 46 | configuring UART2 and setting the UART2 transfer interrupt, employing this
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paul@37 | 47 | interrupt condition for DMA1, produces the same effect.
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paul@37 | 48 |
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paul@37 | 49 | * An external interrupt such as INT2 can be configured, and the peripheral
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paul@37 | 50 | clock can be routed through the CLKO pin and back into the microcontroller
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paul@37 | 51 | via an appropriate pin. With INT2 being employed as the interrupt
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paul@37 | 52 | condition for DMA1, the same effect is produced.
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paul@37 | 53 |
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paul@37 | 54 | Hardware Details
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paul@37 | 55 | ================
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paul@37 | 56 |
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paul@37 | 57 | The pin usage of this solution is documented below.
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paul@37 | 58 |
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paul@37 | 59 | PIC32MX270F256B-50I/SP Pin Assignments
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paul@37 | 60 | --------------------------------------
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paul@37 | 61 |
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paul@37 | 62 | MCLR# 1 \/ 28
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paul@37 | 63 | HSYNC/OC1/RA0 2 27
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paul@37 | 64 | VSYNC/OC2/RA1 3 26 RB15/U1TX
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paul@37 | 65 | D0/RB0 4 25 RB14
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paul@37 | 66 | D1/RB1 5 24 RB13/U1RX
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paul@37 | 67 | D2/RB2 6 23
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paul@37 | 68 | D3/RB3 7 22 RB11/PGEC2
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paul@37 | 69 | 8 21 RB10/PGEC3
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paul@37 | 70 | RA2 9 20
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paul@37 | 71 | RA3 10 19
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paul@37 | 72 | D4/RB4 11 18 RB9
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paul@37 | 73 | 12 17 RB8
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paul@37 | 74 | 13 16 RB7/D7
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paul@37 | 75 | D5/RB5 14 15
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paul@37 | 76 |
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paul@37 | 77 | Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
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paul@37 | 78 | unlike the MX170 variant).
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paul@37 | 79 |
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paul@37 | 80 | UART Connections
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paul@37 | 81 | ----------------
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paul@37 | 82 |
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paul@37 | 83 | UART1 is exposed by the RB13 and RB15 pins.
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paul@37 | 84 |
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paul@37 | 85 | Data Signal Routing
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paul@37 | 86 | -------------------
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paul@37 | 87 |
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paul@37 | 88 | For one bit of intensity, two bits per colour channel:
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paul@37 | 89 |
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paul@37 | 90 | D7 -> 2200R -> I
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paul@37 | 91 |
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paul@37 | 92 | I -> diode -> R
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paul@37 | 93 | I -> diode -> G
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paul@37 | 94 | I -> diode -> B
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paul@37 | 95 |
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paul@37 | 96 | D6 (not connected)
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paul@37 | 97 |
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paul@37 | 98 | D5 -> 470R -> R
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paul@37 | 99 | D4 -> 1000R -> R
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paul@37 | 100 | D3 -> 470R -> G
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paul@37 | 101 | D2 -> 1000R -> G
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paul@37 | 102 | D1 -> 470R -> B
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paul@37 | 103 | D0 -> 1000R -> B
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paul@37 | 104 |
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paul@37 | 105 | HSYNC -> HS
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paul@37 | 106 | VSYNC -> VS
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paul@37 | 107 |
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paul@37 | 108 | Output Socket Pinout
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paul@37 | 109 | --------------------
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paul@37 | 110 |
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paul@37 | 111 | 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R)
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paul@37 | 112 |
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paul@37 | 113 | 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND)
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paul@37 | 114 |
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paul@37 | 115 | 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC)
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paul@37 | 116 |
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paul@37 | 117 | Output Cable Pinout
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paul@37 | 118 | -------------------
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paul@37 | 119 |
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paul@37 | 120 | 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND)
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paul@37 | 121 |
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paul@37 | 122 | 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND)
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paul@37 | 123 |
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paul@37 | 124 | 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC)
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paul@37 | 125 |
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paul@37 | 126 | References
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paul@37 | 127 | ----------
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paul@37 | 128 |
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paul@37 | 129 | https://en.wikipedia.org/wiki/VGA_connector
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paul@37 | 130 |
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paul@37 | 131 | http://papilio.cc/index.php?n=Papilio.VGAWing
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paul@37 | 132 |
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paul@37 | 133 | http://lucidscience.com/pro-vga%20video%20generator-2.aspx
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paul@37 | 134 |
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paul@37 | 135 | https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga
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