paul@0 | 1 | #include "pic32_c.h" |
paul@0 | 2 | #include "init.h" |
paul@11 | 3 | #include "debug.h" |
paul@0 | 4 | |
paul@3 | 5 | static const char message[] = "Hello!\r\n"; |
paul@11 | 6 | static int uart_echo = 0; |
paul@0 | 7 | |
paul@0 | 8 | static void blink(uint32_t delay, uint32_t port, uint32_t pins) |
paul@0 | 9 | { |
paul@0 | 10 | uint32_t counter; |
paul@0 | 11 | |
paul@0 | 12 | /* Clear outputs (LED). */ |
paul@0 | 13 | |
paul@0 | 14 | CLR_REG(port, pins); |
paul@0 | 15 | |
paul@0 | 16 | while (1) |
paul@0 | 17 | { |
paul@0 | 18 | counter = delay; |
paul@0 | 19 | |
paul@0 | 20 | while (counter--) __asm__(""); /* retain loop */ |
paul@0 | 21 | |
paul@0 | 22 | /* Invert outputs (LED). */ |
paul@0 | 23 | |
paul@0 | 24 | INV_REG(port, pins); |
paul@0 | 25 | } |
paul@0 | 26 | } |
paul@0 | 27 | |
paul@0 | 28 | void main(void) |
paul@0 | 29 | { |
paul@0 | 30 | init_memory(); |
paul@0 | 31 | init_pins(); |
paul@0 | 32 | init_outputs(); |
paul@0 | 33 | |
paul@0 | 34 | unlock_config(); |
paul@0 | 35 | config_uart(); |
paul@0 | 36 | lock_config(); |
paul@0 | 37 | |
paul@11 | 38 | init_dma(); |
paul@3 | 39 | |
paul@11 | 40 | /* Initiate DMA on UART receive interrupt, raising transfer completion |
paul@11 | 41 | interrupt. Since the channel is not auto-enabled, it must be explicitly |
paul@11 | 42 | enabled upon completion. */ |
paul@11 | 43 | |
paul@11 | 44 | dma_init(0, 3); |
paul@11 | 45 | dma_set_interrupt(0, U1RX, 1); |
paul@11 | 46 | dma_set_transfer(0, PHYSICAL((uint32_t) message), sizeof(message) - 1, |
paul@3 | 47 | HW_PHYSICAL(UART_REG(1, UxTXREG)), 1, |
paul@3 | 48 | 1); |
paul@11 | 49 | dma_init_interrupt(0, 0b00001000, 7, 3); |
paul@3 | 50 | dma_on(0); |
paul@3 | 51 | |
paul@11 | 52 | /* Set UART interrupt priority below CPU priority. */ |
paul@3 | 53 | |
paul@3 | 54 | uart_init(1, 115200); |
paul@11 | 55 | uart_init_interrupt(1, UxRIF, 1, 3); |
paul@3 | 56 | uart_on(1); |
paul@0 | 57 | |
paul@0 | 58 | interrupts_on(); |
paul@0 | 59 | |
paul@0 | 60 | blink(3 << 24, PORTA, 1 << 3); |
paul@0 | 61 | } |
paul@0 | 62 | |
paul@0 | 63 | void exception_handler(void) |
paul@0 | 64 | { |
paul@0 | 65 | blink(3 << 12, PORTA, 1 << 3); |
paul@0 | 66 | } |
paul@0 | 67 | |
paul@0 | 68 | void interrupt_handler(void) |
paul@0 | 69 | { |
paul@11 | 70 | uint32_t ifs, val; |
paul@11 | 71 | |
paul@3 | 72 | /* Check for a UART receive interrupt condition (UxRIF). */ |
paul@0 | 73 | |
paul@11 | 74 | ifs = REG(UARTIFS) & UART_INT_FLAGS(1, UxRIF); |
paul@8 | 75 | |
paul@8 | 76 | if (ifs) |
paul@3 | 77 | { |
paul@8 | 78 | /* Clear the UART interrupt condition. */ |
paul@8 | 79 | |
paul@8 | 80 | CLR_REG(UARTIFS, ifs); |
paul@8 | 81 | |
paul@3 | 82 | /* Write the received data back. */ |
paul@0 | 83 | |
paul@3 | 84 | while (REG(UART_REG(1, UxSTA)) & 1) |
paul@11 | 85 | { |
paul@11 | 86 | val = REG(UART_REG(1, UxRXREG)); |
paul@11 | 87 | if (uart_echo) |
paul@11 | 88 | uart_write((char) val); |
paul@11 | 89 | } |
paul@11 | 90 | } |
paul@11 | 91 | |
paul@11 | 92 | /* Check for a DMA interrupt condition (CHBCIF). */ |
paul@0 | 93 | |
paul@11 | 94 | ifs = REG(DMAIFS) & DMA_INT_FLAGS(0, 1); |
paul@11 | 95 | |
paul@11 | 96 | if (ifs) |
paul@11 | 97 | { |
paul@3 | 98 | INV_REG(PORTA, 1 << 2); |
paul@11 | 99 | CLR_REG(DMA_REG(0, DCHxINT), 0b11111111); |
paul@11 | 100 | CLR_REG(DMAIFS, ifs); |
paul@11 | 101 | |
paul@11 | 102 | dma_on(0); |
paul@3 | 103 | } |
paul@0 | 104 | } |