paul@145 | 1 | = VGA Signal Output = |
paul@144 | 2 | |
paul@149 | 3 | A number of [[VGA Output Examples|examples]] demonstrate VGA signal generation |
paul@149 | 4 | from a PIC32 microcontroller. These examples employ a particular [[VGA Signal |
paul@149 | 5 | Wiring|wiring scheme]] in order to deliver signals to a suitable display or |
paul@149 | 6 | monitor. |
paul@149 | 7 | |
paul@149 | 8 | Within the microcontroller, there are two principal mechanisms demonstrated in |
paul@149 | 9 | this project for generating a VGA signal: |
paul@144 | 10 | |
paul@144 | 11 | * Using the CPU to "copy" pixel data to an output port |
paul@144 | 12 | * Using DMA transfers to "copy" pixel data to an output port |
paul@144 | 13 | |
paul@144 | 14 | Within the latter, there are a number of variations in the mechanism employed: |
paul@144 | 15 | |
paul@144 | 16 | * Use of general-purpose output pins versus parallel mode outputs |
paul@144 | 17 | * Use of large transfer cells containing each entire pixel line versus small |
paul@144 | 18 | transfer cells containing fragments of each line |
paul@144 | 19 | * Use of a single transfer-initiating event versus separate line-initiating |
paul@144 | 20 | and transfer-initiating events |
paul@144 | 21 | |
paul@144 | 22 | == Using the CPU for Transfers == |
paul@144 | 23 | |
paul@144 | 24 | {{{#!graphviz |
paul@144 | 25 | //format=svg |
paul@144 | 26 | //transform=notugly |
paul@144 | 27 | digraph cpu { |
paul@153 | 28 | node [shape=box,fontsize="13.0",fontname="sans-serif"]; |
paul@144 | 29 | rankdir=TD; |
paul@144 | 30 | |
paul@144 | 31 | subgraph { |
paul@144 | 32 | rank=same; |
paul@144 | 33 | |
paul@144 | 34 | timer [label="Display line\ntimer",style=filled,fillcolor=gold]; |
paul@144 | 35 | t_0 [label="0",shape=ellipse]; |
paul@144 | 36 | t_hsync [label="hsync",shape=ellipse]; |
paul@144 | 37 | t_limit [label="limit",shape=ellipse]; |
paul@144 | 38 | } |
paul@144 | 39 | |
paul@144 | 40 | oc1 [label="Output compare",style=filled,fillcolor=gold]; |
paul@144 | 41 | |
paul@144 | 42 | subgraph { |
paul@144 | 43 | rank=same; |
paul@144 | 44 | |
paul@144 | 45 | lineirq [label="Display line\ninterrupt handler"]; |
paul@144 | 46 | pixelirq [label="Pixel output\ninterrupt handler"]; |
paul@144 | 47 | } |
paul@144 | 48 | |
paul@144 | 49 | subgraph { |
paul@144 | 50 | rank=same; |
paul@144 | 51 | |
paul@144 | 52 | pixels [label="Pixel output\nBlack/reset output",style=filled,fillcolor=green,shape=parallelogram]; |
paul@144 | 53 | hsync [label="Horizontal sync",shape=house,style=filled,fillcolor=red]; |
paul@144 | 54 | vsync [label="Vertical sync",shape=house,style=filled,fillcolor=red]; |
paul@144 | 55 | } |
paul@144 | 56 | |
paul@144 | 57 | /* The timer starts at 0 and wraps around at limit. */ |
paul@144 | 58 | |
paul@144 | 59 | timer -> t_0 [arrowhead=none]; |
paul@144 | 60 | t_0 -> t_hsync -> t_limit -> t_0 [style=dashed]; |
paul@144 | 61 | |
paul@144 | 62 | /* The timer initiates the interrupt request for pixel production. */ |
paul@144 | 63 | |
paul@144 | 64 | t_0 -> pixelirq; |
paul@144 | 65 | |
paul@144 | 66 | /* The interrupt handler generates the pixel output. */ |
paul@144 | 67 | |
paul@144 | 68 | pixelirq -> pixels; |
paul@144 | 69 | |
paul@144 | 70 | /* The timer feeds the output compare unit, driving hsync. */ |
paul@144 | 71 | |
paul@144 | 72 | t_hsync -> oc1; |
paul@144 | 73 | oc1 -> hsync; |
paul@144 | 74 | |
paul@144 | 75 | /* The output compare unit initiates the interrupt request for each line, |
paul@144 | 76 | driving vsync. */ |
paul@144 | 77 | |
paul@144 | 78 | oc1 -> lineirq; |
paul@144 | 79 | lineirq -> vsync; |
paul@144 | 80 | } |
paul@144 | 81 | }}} |
paul@144 | 82 | |
paul@144 | 83 | == Using DMA for Transfers == |
paul@144 | 84 | |
paul@144 | 85 | {{{#!graphviz |
paul@144 | 86 | //format=svg |
paul@144 | 87 | //transform=notugly |
paul@144 | 88 | digraph dma { |
paul@153 | 89 | node [shape=box,fontsize="13.0",fontname="sans-serif"]; |
paul@144 | 90 | rankdir=TD; |
paul@144 | 91 | |
paul@144 | 92 | subgraph { |
paul@144 | 93 | rank=same; |
paul@144 | 94 | |
paul@144 | 95 | timer [label="Display line\ntimer",style=filled,fillcolor=gold]; |
paul@144 | 96 | t_0 [label="0",shape=ellipse]; |
paul@144 | 97 | t_hsync [label="hsync",shape=ellipse]; |
paul@144 | 98 | t_limit [label="limit",shape=ellipse]; |
paul@144 | 99 | } |
paul@144 | 100 | |
paul@144 | 101 | oc1 [label="Output compare",style=filled,fillcolor=gold]; |
paul@144 | 102 | |
paul@144 | 103 | subgraph { |
paul@144 | 104 | rank=same; |
paul@144 | 105 | |
paul@144 | 106 | dma_line [label="Pixel output\nDMA channel",style=filled,fillcolor=lightblue]; |
paul@144 | 107 | dma_reset [label="Pixel reset\nDMA channel",style=filled,fillcolor=lightblue]; |
paul@144 | 108 | lineirq [label="Display line\ninterrupt handler"]; |
paul@144 | 109 | } |
paul@144 | 110 | |
paul@144 | 111 | subgraph { |
paul@144 | 112 | rank=same; |
paul@144 | 113 | |
paul@144 | 114 | pixels [label="Pixel output",style=filled,fillcolor=green,shape=parallelogram]; |
paul@144 | 115 | black [label="Black/reset output",style=filled,fillcolor=black,fontcolor=white,shape=parallelogram]; |
paul@144 | 116 | hsync [label="Horizontal sync",shape=house,style=filled,fillcolor=red]; |
paul@144 | 117 | vsync [label="Vertical sync",shape=house,style=filled,fillcolor=red]; |
paul@144 | 118 | } |
paul@144 | 119 | |
paul@144 | 120 | /* The timer starts at 0 and wraps around at limit. */ |
paul@144 | 121 | |
paul@144 | 122 | timer -> t_0 [arrowhead=none]; |
paul@144 | 123 | t_0 -> t_hsync -> t_limit -> t_0 [style=dashed]; |
paul@144 | 124 | |
paul@144 | 125 | /* The timer initiates the DMA transfer for pixel production. */ |
paul@144 | 126 | |
paul@144 | 127 | t_0 -> dma_line; |
paul@144 | 128 | |
paul@144 | 129 | /* The line channel generates the pixel output. */ |
paul@144 | 130 | |
paul@144 | 131 | dma_line -> pixels; |
paul@144 | 132 | |
paul@144 | 133 | /* The completion of the line channel initiates the reset channel. */ |
paul@144 | 134 | |
paul@144 | 135 | dma_line -> dma_reset; |
paul@144 | 136 | |
paul@144 | 137 | /* The reset channel generates black/reset output. */ |
paul@144 | 138 | |
paul@144 | 139 | dma_reset -> black; |
paul@144 | 140 | |
paul@144 | 141 | /* The black/reset value follows the visible pixels. */ |
paul@144 | 142 | |
paul@144 | 143 | pixels -> black [style=dashed]; |
paul@144 | 144 | |
paul@144 | 145 | /* The timer feeds the output compare unit, driving hsync. */ |
paul@144 | 146 | |
paul@144 | 147 | t_hsync -> oc1; |
paul@144 | 148 | oc1 -> hsync; |
paul@144 | 149 | |
paul@144 | 150 | /* The output compare unit initiates the interrupt request for each line, |
paul@144 | 151 | driving vsync. */ |
paul@144 | 152 | |
paul@144 | 153 | oc1 -> lineirq; |
paul@144 | 154 | lineirq -> vsync; |
paul@144 | 155 | } |
paul@144 | 156 | }}} |
paul@144 | 157 | |
paul@144 | 158 | == Using DMA and Timed Transfers == |
paul@144 | 159 | |
paul@144 | 160 | {{{#!graphviz |
paul@144 | 161 | //format=svg |
paul@144 | 162 | //transform=notugly |
paul@144 | 163 | digraph dma { |
paul@153 | 164 | node [shape=box,fontsize="13.0",fontname="sans-serif"]; |
paul@144 | 165 | rankdir=TD; |
paul@144 | 166 | |
paul@144 | 167 | subgraph { |
paul@144 | 168 | rank=same; |
paul@144 | 169 | |
paul@144 | 170 | timer [label="Display line\ntimer",style=filled,fillcolor=gold]; |
paul@144 | 171 | t_0 [label="0",shape=ellipse]; |
paul@144 | 172 | t_hsync [label="hsync",shape=ellipse]; |
paul@144 | 173 | t_limit [label="limit",shape=ellipse]; |
paul@144 | 174 | } |
paul@144 | 175 | |
paul@144 | 176 | oc1 [label="Output compare",style=filled,fillcolor=gold]; |
paul@144 | 177 | |
paul@144 | 178 | subgraph { |
paul@144 | 179 | rank=same; |
paul@144 | 180 | |
paul@144 | 181 | trtimer [label="Transfer timer",style=filled,fillcolor=gold]; |
paul@144 | 182 | tr_0 [label="0",shape=ellipse]; |
paul@144 | 183 | tr_limit [label="limit",shape=ellipse]; |
paul@144 | 184 | } |
paul@144 | 185 | |
paul@144 | 186 | subgraph { |
paul@144 | 187 | rank=same; |
paul@144 | 188 | |
paul@144 | 189 | dma_init [label="Initiator\nDMA channel",style=filled,fillcolor=lightblue]; |
paul@144 | 190 | dma_line [label="Pixel output\nDMA channel",style=filled,fillcolor=lightblue]; |
paul@144 | 191 | dma_reset [label="Pixel reset\nDMA channel",style=filled,fillcolor=lightblue]; |
paul@144 | 192 | lineirq [label="Display line\ninterrupt handler"]; |
paul@144 | 193 | } |
paul@144 | 194 | |
paul@144 | 195 | subgraph { |
paul@144 | 196 | rank=same; |
paul@144 | 197 | |
paul@144 | 198 | pixels [label="Pixel output",style=filled,fillcolor=green,shape=parallelogram]; |
paul@144 | 199 | black [label="Black/reset output",style=filled,fillcolor=black,fontcolor=white,shape=parallelogram]; |
paul@144 | 200 | hsync [label="Horizontal sync",shape=house,style=filled,fillcolor=red]; |
paul@144 | 201 | vsync [label="Vertical sync",shape=house,style=filled,fillcolor=red]; |
paul@144 | 202 | } |
paul@144 | 203 | |
paul@144 | 204 | /* The line timer starts at 0 and wraps around at limit. */ |
paul@144 | 205 | |
paul@144 | 206 | timer -> t_0 [arrowhead=none]; |
paul@144 | 207 | t_0 -> t_hsync -> t_limit -> t_0 [style=dashed]; |
paul@144 | 208 | |
paul@144 | 209 | /* The transfer timer starts at 0 and wraps around at limit. */ |
paul@144 | 210 | |
paul@144 | 211 | trtimer -> tr_0 [arrowhead=none]; |
paul@144 | 212 | tr_0 -> tr_limit -> tr_0 [style=dashed]; |
paul@144 | 213 | |
paul@144 | 214 | /* The line timer initiates the DMA transfers for the display line. */ |
paul@144 | 215 | |
paul@144 | 216 | t_0 -> dma_init; |
paul@144 | 217 | |
paul@144 | 218 | /* The completion of the initiating channel enables the line channel. */ |
paul@144 | 219 | |
paul@144 | 220 | dma_init -> dma_line; |
paul@144 | 221 | |
paul@144 | 222 | /* Each cell transfer in the line channel is initiated by the transfer |
paul@144 | 223 | timer. */ |
paul@144 | 224 | |
paul@144 | 225 | tr_0 -> dma_line; |
paul@144 | 226 | |
paul@144 | 227 | /* The line channel generates the pixel output. */ |
paul@144 | 228 | |
paul@144 | 229 | dma_line -> pixels; |
paul@144 | 230 | |
paul@144 | 231 | /* The completion of the line channel initiates the reset channel. */ |
paul@144 | 232 | |
paul@144 | 233 | dma_line -> dma_reset; |
paul@144 | 234 | |
paul@144 | 235 | /* The reset channel generates black/reset output. */ |
paul@144 | 236 | |
paul@144 | 237 | dma_reset -> black; |
paul@144 | 238 | |
paul@144 | 239 | /* The black/reset value follows the visible pixels. */ |
paul@144 | 240 | |
paul@144 | 241 | pixels -> black [style=dashed]; |
paul@144 | 242 | |
paul@144 | 243 | /* The timer feeds the output compare unit, driving hsync. */ |
paul@144 | 244 | |
paul@144 | 245 | t_hsync -> oc1; |
paul@144 | 246 | oc1 -> hsync; |
paul@144 | 247 | |
paul@144 | 248 | /* The output compare unit initiates the interrupt request for each line, |
paul@144 | 249 | driving vsync. */ |
paul@144 | 250 | |
paul@144 | 251 | oc1 -> lineirq; |
paul@144 | 252 | lineirq -> vsync; |
paul@144 | 253 | } |
paul@144 | 254 | }}} |
paul@144 | 255 | |
paul@144 | 256 | == Using DMA and Timed Dual-Channel Transfers == |
paul@144 | 257 | |
paul@144 | 258 | {{{#!graphviz |
paul@144 | 259 | //format=svg |
paul@144 | 260 | //transform=notugly |
paul@144 | 261 | digraph dma { |
paul@153 | 262 | node [shape=box,fontsize="13.0",fontname="sans-serif"]; |
paul@144 | 263 | rankdir=TD; |
paul@144 | 264 | |
paul@144 | 265 | subgraph { |
paul@144 | 266 | rank=same; |
paul@144 | 267 | |
paul@144 | 268 | timer [label="Display line\ntimer",style=filled,fillcolor=gold]; |
paul@144 | 269 | t_0 [label="0",shape=ellipse]; |
paul@144 | 270 | t_hsync [label="hsync",shape=ellipse]; |
paul@144 | 271 | t_limit [label="limit",shape=ellipse]; |
paul@144 | 272 | } |
paul@144 | 273 | |
paul@144 | 274 | oc1 [label="Output compare",style=filled,fillcolor=gold]; |
paul@144 | 275 | |
paul@144 | 276 | subgraph { |
paul@144 | 277 | rank=same; |
paul@144 | 278 | |
paul@144 | 279 | trtimer [label="Transfer timer",style=filled,fillcolor=gold]; |
paul@144 | 280 | tr_0 [label="0",shape=ellipse]; |
paul@144 | 281 | tr_limit [label="limit",shape=ellipse]; |
paul@144 | 282 | } |
paul@144 | 283 | |
paul@144 | 284 | subgraph { |
paul@144 | 285 | rank=same; |
paul@144 | 286 | |
paul@144 | 287 | dma_init [label="Initiator\nDMA channel",style=filled,fillcolor=lightblue]; |
paul@144 | 288 | dma_line [label="{Pixel output\nDMA channel #1 | Pixel output\nDMA channel #2}",style=filled,fillcolor=lightblue,shape=record]; |
paul@144 | 289 | dma_reset [label="Pixel reset\nDMA channel",style=filled,fillcolor=lightblue]; |
paul@144 | 290 | lineirq [label="Display line\ninterrupt handler"]; |
paul@144 | 291 | } |
paul@144 | 292 | |
paul@144 | 293 | subgraph { |
paul@144 | 294 | rank=same; |
paul@144 | 295 | |
paul@144 | 296 | pixels [label="Pixel output",style=filled,fillcolor=green,shape=parallelogram]; |
paul@144 | 297 | black [label="Black/reset output",style=filled,fillcolor=black,fontcolor=white,shape=parallelogram]; |
paul@144 | 298 | hsync [label="Horizontal sync",shape=house,style=filled,fillcolor=red]; |
paul@144 | 299 | vsync [label="Vertical sync",shape=house,style=filled,fillcolor=red]; |
paul@144 | 300 | } |
paul@144 | 301 | |
paul@144 | 302 | /* The line timer starts at 0 and wraps around at limit. */ |
paul@144 | 303 | |
paul@144 | 304 | timer -> t_0 [arrowhead=none]; |
paul@144 | 305 | t_0 -> t_hsync -> t_limit -> t_0 [style=dashed]; |
paul@144 | 306 | |
paul@144 | 307 | /* The transfer timer starts at 0 and wraps around at limit. */ |
paul@144 | 308 | |
paul@144 | 309 | trtimer -> tr_0 [arrowhead=none]; |
paul@144 | 310 | tr_0 -> tr_limit -> tr_0 [style=dashed]; |
paul@144 | 311 | |
paul@144 | 312 | /* The line timer initiates the DMA transfers for the display line. */ |
paul@144 | 313 | |
paul@144 | 314 | t_0 -> dma_init; |
paul@144 | 315 | |
paul@144 | 316 | /* The completion of the initiating channel enables the line channels. */ |
paul@144 | 317 | |
paul@144 | 318 | dma_init -> dma_line; |
paul@144 | 319 | |
paul@144 | 320 | /* Each cell transfer in the line channels is initiated by the transfer |
paul@144 | 321 | timer. */ |
paul@144 | 322 | |
paul@144 | 323 | tr_0 -> dma_line; |
paul@144 | 324 | |
paul@144 | 325 | /* The line channels generate the pixel output. */ |
paul@144 | 326 | |
paul@144 | 327 | dma_line -> pixels; |
paul@144 | 328 | |
paul@144 | 329 | /* The completion of the line channels initiates the reset channel. */ |
paul@144 | 330 | |
paul@144 | 331 | dma_line -> dma_reset; |
paul@144 | 332 | |
paul@144 | 333 | /* The reset channel generates black/reset output. */ |
paul@144 | 334 | |
paul@144 | 335 | dma_reset -> black; |
paul@144 | 336 | |
paul@144 | 337 | /* The black/reset value follows the visible pixels. */ |
paul@144 | 338 | |
paul@144 | 339 | pixels -> black [style=dashed]; |
paul@144 | 340 | |
paul@144 | 341 | /* The timer feeds the output compare unit, driving hsync. */ |
paul@144 | 342 | |
paul@144 | 343 | t_hsync -> oc1; |
paul@144 | 344 | oc1 -> hsync; |
paul@144 | 345 | |
paul@144 | 346 | /* The output compare unit initiates the interrupt request for each line, |
paul@144 | 347 | driving vsync. */ |
paul@144 | 348 | |
paul@144 | 349 | oc1 -> lineirq; |
paul@144 | 350 | lineirq -> vsync; |
paul@144 | 351 | } |
paul@144 | 352 | }}} |