paul@149 | 1 | = Demo Example = |
paul@149 | 2 | |
paul@149 | 3 | This example demonstrates UART communication using UART1. Interrupt conditions |
paul@149 | 4 | on the UART peripheral are handled, input is tested, output is produced, and |
paul@149 | 5 | upon receiving the `0` character, DMA-driven output is initiated. |
paul@149 | 6 | |
paul@149 | 7 | The DMA-driven output demonstrates mechanisms employed by some of the [[VGA |
paul@149 | 8 | Output Examples|VGA examples]]. A channel is enabled by the interrupt handler |
paul@149 | 9 | and its transfers each initiated by a timer; this should cause text to be |
paul@149 | 10 | transmitted relatively slowly across the serial connection... |
paul@149 | 11 | |
paul@149 | 12 | {{{ |
paul@149 | 13 | Hello! |
paul@149 | 14 | }}} |
paul@149 | 15 | |
paul@149 | 16 | When this first channel completes all transfers, two other channels chained to |
paul@149 | 17 | it are enabled. Another timer then causes their transfers to be initiated. |
paul@149 | 18 | Since these two channels effectively compete for access to the UART |
paul@149 | 19 | peripheral, their transfers are interleaved. Regardless of the configuration |
paul@149 | 20 | of the example, more text should be transmitted relatively slowly... |
paul@149 | 21 | |
paul@149 | 22 | {{{ |
paul@149 | 23 | And once again, hello! |
paul@149 | 24 | }}} |
paul@149 | 25 | |
paul@149 | 26 | Although such DMA channel interleaving is rather exotic, other techniques |
paul@149 | 27 | employed by the example are likely to be applicable elsewhere. |
paul@149 | 28 | |
paul@149 | 29 | == Hardware Details == |
paul@149 | 30 | |
paul@149 | 31 | The pin usage of this solution is documented below. |
paul@149 | 32 | |
paul@149 | 33 | === PIC32MX270F256B-50I/SP Pin Assignments === |
paul@149 | 34 | |
paul@149 | 35 | {{{ |
paul@149 | 36 | MCLR# 1 \/ 28 |
paul@149 | 37 | RA0 2 27 |
paul@149 | 38 | RA1 3 26 RB15/U1TX |
paul@149 | 39 | RB0 4 25 RB14 |
paul@149 | 40 | RB1 5 24 RB13/U1RX |
paul@149 | 41 | RB2 6 23 |
paul@149 | 42 | RB3 7 22 RB11/PGEC2 |
paul@154 | 43 | 8 21 RB10/PGED2 |
paul@149 | 44 | RA2 9 20 |
paul@149 | 45 | RA3 10 19 |
paul@149 | 46 | RB4 11 18 RB9 |
paul@149 | 47 | 12 17 RB8 |
paul@149 | 48 | 13 16 RB7 |
paul@149 | 49 | RB5 14 15 |
paul@149 | 50 | }}} |
paul@149 | 51 | |
paul@149 | 52 | Note that RB6 is not available on pin 15 on this device (it is needed for VBUS |
paul@149 | 53 | unlike the MX170 variant). |
paul@149 | 54 | |
paul@149 | 55 | === UART Connections === |
paul@149 | 56 | |
paul@149 | 57 | UART1 is exposed by the RB13 and RB15 pins. |