paul@148 | 1 | = VGA Output Example (Parallel Mode Transfers) = |
paul@148 | 2 | |
paul@149 | 3 | This example demonstrates the generation of an analogue [[VGA Signal Output| |
paul@149 | 4 | VGA]] signal from a PIC32 microcontroller using the parallel mode (parallel |
paul@149 | 5 | master port, PMP) peripheral. The result is not entirely satisfactory: |
paul@148 | 6 | |
paul@148 | 7 | * Pixels are very narrow unless buffered using a flip-flop driven by the |
paul@148 | 8 | peripheral, this being a characteristic of the way the peripheral works, it |
paul@148 | 9 | normally being used to drive memory and display controllers. |
paul@148 | 10 | |
paul@148 | 11 | * Introducing a flip-flop means that the final pixel from the pixel data |
paul@148 | 12 | remains asserted and must be reset using a second DMA channel. |
paul@148 | 13 | |
paul@148 | 14 | * Every fourth pixel is wider than the others, this apparently being an |
paul@148 | 15 | artefact of the DMA transfer mechanism. |
paul@148 | 16 | |
paul@148 | 17 | It might be possible introduce some kind of delay to the write strobe (PMWR) |
paul@148 | 18 | and even out the pixel widths, but this has not been investigated. |
paul@148 | 19 | |
paul@148 | 20 | It appears to be the case that the system and peripheral clock frequencies |
paul@148 | 21 | need to be matched. In this example, a frequency of 48MHz has been chosen. |
paul@148 | 22 | |
paul@148 | 23 | == Hardware Details == |
paul@148 | 24 | |
paul@148 | 25 | The pin usage of this solution is documented below. |
paul@148 | 26 | |
paul@148 | 27 | === PIC32MX270F256B-50I/SP Pin Assignments === |
paul@148 | 28 | |
paul@148 | 29 | {{{ |
paul@148 | 30 | MCLR# 1 \/ 28 |
paul@148 | 31 | D7/PMD7/RA0 2 27 |
paul@148 | 32 | D6/PMD6/RA1 3 26 RB15/U1TX |
paul@148 | 33 | D0/PMD0/RB0 4 25 RB14 |
paul@148 | 34 | D1/PMD1/RB1 5 24 RB13/(PMRD)/U1RX |
paul@148 | 35 | D2/PMD2/RB2 6 23 |
paul@148 | 36 | PMWR/RB3 7 22 RB11/PGEC2 |
paul@154 | 37 | 8 21 RB10/PGED2 |
paul@148 | 38 | RA2 9 20 |
paul@148 | 39 | (PMA0)/RA3 10 19 |
paul@148 | 40 | HSYNC/OC1/RB4 11 18 RB9/PMD3/D3 |
paul@148 | 41 | 12 17 RB8/PMD4/D4 |
paul@148 | 42 | 13 16 RB7/PMD5/D5 |
paul@148 | 43 | VSYNC/OC2/RB5 14 15 |
paul@148 | 44 | }}} |
paul@148 | 45 | |
paul@148 | 46 | Note that RB6 is not available on pin 15 on this device (it is needed for VBUS |
paul@148 | 47 | unlike the MX170 variant). |
paul@148 | 48 | |
paul@148 | 49 | === UART Connections === |
paul@148 | 50 | |
paul@148 | 51 | UART1 is exposed by the RB13 and RB15 pins. |
paul@148 | 52 | |
paul@148 | 53 | === Data Signal Routing === |
paul@148 | 54 | |
paul@148 | 55 | A flip-flop is used to buffer the outputs: |
paul@148 | 56 | |
paul@148 | 57 | {{{ |
paul@148 | 58 | Dn -> 74HC273:Dn |
paul@148 | 59 | 74HC273:Qn -> Qn |
paul@148 | 60 | VCC -> 74HC273:MR# |
paul@148 | 61 | PMWR -> 74HC273:CP |
paul@148 | 62 | }}} |
paul@148 | 63 | |
paul@148 | 64 | For two bits of intensity, two bits per colour channel: |
paul@148 | 65 | |
paul@148 | 66 | {{{ |
paul@148 | 67 | Q7 -> 2200R -> I |
paul@148 | 68 | Q6 -> 4700R -> I |
paul@148 | 69 | |
paul@148 | 70 | I -> diode -> R |
paul@148 | 71 | I -> diode -> G |
paul@148 | 72 | I -> diode -> B |
paul@148 | 73 | |
paul@148 | 74 | Q5 -> 470R -> R |
paul@148 | 75 | Q4 -> 1000R -> R |
paul@148 | 76 | Q3 -> 470R -> G |
paul@148 | 77 | Q2 -> 1000R -> G |
paul@148 | 78 | Q1 -> 470R -> B |
paul@148 | 79 | Q0 -> 1000R -> B |
paul@148 | 80 | |
paul@148 | 81 | HSYNC -> HS |
paul@148 | 82 | VSYNC -> VS |
paul@148 | 83 | }}} |