CommonPIC32

Annotated docs/wiki/Examples--vga-timer

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2019-05-04 Paul Boddie file changeset files shortlog Moved VGA example documentation into the wiki documentation.
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= VGA Output Example (Timed DMA Transfers) =
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This example demonstrates the generation of an analogue VGA signal from a
 
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PIC32 microcontroller using general output pins. Unlike the [[../vga|vga]] and
 
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[[../vga-pmp|vga-pmp]] examples, it employs a regular interrupt condition to
 
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schedule single-byte (single-pixel) DMA transfers instead of a single
 
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whole-line transfer.
 
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The principal advantage of this method over the whole-line transfer method is
 
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its production of pixels with consistent widths. The principal disadvantage is
 
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the significant loss of horizontal resolution due to the latencies involved in
 
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propagating interrupt conditions to the DMA controller and thereby initiating
 
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each transfer.
 
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Employing a peripheral clock that has half the frequency of the system clock
 
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should ensure the stability of the picture, since the lower frequency may make
 
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transfers easier to schedule. The peripheral clock should provide a more
 
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forgiving deadline for each transfer, permitting late transfers to complete on
 
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time.
 
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Meanwhile, matching the system and peripheral clock frequencies appears to
 
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leave the scheduling of transfers open to uncertainty, with transfers being
 
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more readily delayed by other activity in the system, and with instability of
 
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the picture being the result.
 
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Unlike the [[../vga|vga]] example, but in common with the
 
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[[../vga-dual|vga-dual]] example, this example employs two DMA channels for
 
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pixel data which are interleaved to investigate a potential remedy for the
 
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wide pixel effect. This seems to preserve consistent pixel widths only with a
 
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transfer cell size of 1: other cell sizes suffer from the wide pixel problem.
 
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Despite not offering the greater throughput of larger cell sizes, merely
 
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employing dual channels increases throughput for a cell size of 1, making the
 
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technique worth using.
 
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In contrast to the [[../vga|vga]] and [[../vga-pmp|vga-pmp]] examples, a
 
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special DMA channel is employed to initiate the pixel transfer process without
 
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actually transferring any pixel data itself. The channel arrangement is as
 
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follows:
 
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|| Transfer Initiator || DMA Channel || Transfer Activity ||
 
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|| Timer2             || DMA1        || zerodata -> PORTB ||
 
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|| Timer3             || DMA0        || linedata -> PORTB ||
 
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|| Timer3             || DMA2        || linedata -> PORTB ||
 
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|| Timer3             || DMA3        || zerodata -> PORTB ||
 
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The real purpose of this channel (DMA1) is to capture the Timer2 interrupt
 
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condition and to enable the following channels (DMA0, DMA2) through channel
 
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chaining.  Having been enabled, DMA0 and DMA2 are then able to conduct
 
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transfers at a tempo dictated by Timer3. Finally, DMA3 acts as the "reset" or
 
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"zero" channel to ensure that the pixel level is set to black at the end of
 
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each display line.
 
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In principle, other initiating conditions can be used instead of Timer3, which
 
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is configured to produce such conditions as frequently as possible: 
 
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  * A persistent interrupt condition can be employed instead. For example,
 
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    configuring UART2 and setting the UART2 transfer interrupt, employing this
 
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    interrupt condition for DMA0 and DMA2, produces the same effect.
 
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  * An external interrupt such as INT2 can be configured, and the peripheral
 
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    clock can be routed through the CLKO pin and back into the microcontroller
 
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    via an appropriate pin. With INT2 being employed as the interrupt
 
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    condition for DMA0 and DMA2, the same effect is produced.
 
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== Hardware Details ==
 
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The pin usage of this solution is documented below.
 
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=== PIC32MX270F256B-50I/SP Pin Assignments ===
 
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{{{
 
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MCLR#          1  \/  28
 
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HSYNC/OC1/RA0  2      27
 
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VSYNC/OC2/RA1  3      26 RB15/U1TX
 
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       D0/RB0  4      25 RB14
 
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       D1/RB1  5      24 RB13/U1RX
 
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       D2/RB2  6      23
 
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       D3/RB3  7      22 RB11/PGEC2
 
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               8      21 RB10/PGEC3
 
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          RA2  9      20
 
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          RA3 10      19
 
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       D4/RB4 11      18 RB9
 
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              12      17 RB8
 
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              13      16 RB7/D7
 
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       D5/RB5 14      15
 
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}}}
 
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Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
 
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unlike the MX170 variant).
 
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=== UART Connections ===
 
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UART1 is exposed by the RB13 and RB15 pins.
 
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=== Data Signal Routing ===
 
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For one bit of intensity, two bits per colour channel:
 
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{{{
 
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D7 -> 2200R -> I
 
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I -> diode -> R
 
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I -> diode -> G
 
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I -> diode -> B
 
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D6 (not connected)
 
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D5 -> 470R -> R
 
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D4 -> 1000R -> R
 
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D3 -> 470R -> G
 
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D2 -> 1000R -> G
 
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D1 -> 470R -> B
 
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D0 -> 1000R -> B
 
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HSYNC -> HS
 
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VSYNC -> VS
 
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}}}
 
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=== Output Socket Pinout ===
 
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{{{
 
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5 (GND)  4 (NC)   3 (B)    2 (G)    1 (R)
 
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    10 (GND) 9 (NC)   8 (GND)  7 (GND)  6 (GND)
 
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15 (NC)  14 (VS)  13 (HS)  12 (NC)  11 (NC)
 
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}}}
 
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=== Output Cable Pinout ===
 
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{{{
 
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    1 (R)    2 (G)    3 (B)    4 (NC)   5 (GND)
 
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6 (GND)  7 (GND)  8 (GND)  9 (NC)   10 (GND)
 
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    11 (NC)  12 (NC)  13 (HS)  14 (VS)  15 (NC)
 
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}}}
 
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== References ==
 
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https://en.wikipedia.org/wiki/VGA_connector
 
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http://papilio.cc/index.php?n=Papilio.VGAWing
 
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http://lucidscience.com/pro-vga%20video%20generator-2.aspx
 
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https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga