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1.2 +++ b/docs/wiki/Examples--vga-timer Sat May 04 22:54:18 2019 +0200
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1.4 += VGA Output Example (Timed DMA Transfers) =
1.5 +
1.6 +This example demonstrates the generation of an analogue VGA signal from a
1.7 +PIC32 microcontroller using general output pins. Unlike the [[../vga|vga]] and
1.8 +[[../vga-pmp|vga-pmp]] examples, it employs a regular interrupt condition to
1.9 +schedule single-byte (single-pixel) DMA transfers instead of a single
1.10 +whole-line transfer.
1.11 +
1.12 +The principal advantage of this method over the whole-line transfer method is
1.13 +its production of pixels with consistent widths. The principal disadvantage is
1.14 +the significant loss of horizontal resolution due to the latencies involved in
1.15 +propagating interrupt conditions to the DMA controller and thereby initiating
1.16 +each transfer.
1.17 +
1.18 +Employing a peripheral clock that has half the frequency of the system clock
1.19 +should ensure the stability of the picture, since the lower frequency may make
1.20 +transfers easier to schedule. The peripheral clock should provide a more
1.21 +forgiving deadline for each transfer, permitting late transfers to complete on
1.22 +time.
1.23 +
1.24 +Meanwhile, matching the system and peripheral clock frequencies appears to
1.25 +leave the scheduling of transfers open to uncertainty, with transfers being
1.26 +more readily delayed by other activity in the system, and with instability of
1.27 +the picture being the result.
1.28 +
1.29 +Unlike the [[../vga|vga]] example, but in common with the
1.30 +[[../vga-dual|vga-dual]] example, this example employs two DMA channels for
1.31 +pixel data which are interleaved to investigate a potential remedy for the
1.32 +wide pixel effect. This seems to preserve consistent pixel widths only with a
1.33 +transfer cell size of 1: other cell sizes suffer from the wide pixel problem.
1.34 +Despite not offering the greater throughput of larger cell sizes, merely
1.35 +employing dual channels increases throughput for a cell size of 1, making the
1.36 +technique worth using.
1.37 +
1.38 +In contrast to the [[../vga|vga]] and [[../vga-pmp|vga-pmp]] examples, a
1.39 +special DMA channel is employed to initiate the pixel transfer process without
1.40 +actually transferring any pixel data itself. The channel arrangement is as
1.41 +follows:
1.42 +
1.43 +|| Transfer Initiator || DMA Channel || Transfer Activity ||
1.44 +|| Timer2 || DMA1 || zerodata -> PORTB ||
1.45 +|| Timer3 || DMA0 || linedata -> PORTB ||
1.46 +|| Timer3 || DMA2 || linedata -> PORTB ||
1.47 +|| Timer3 || DMA3 || zerodata -> PORTB ||
1.48 +
1.49 +The real purpose of this channel (DMA1) is to capture the Timer2 interrupt
1.50 +condition and to enable the following channels (DMA0, DMA2) through channel
1.51 +chaining. Having been enabled, DMA0 and DMA2 are then able to conduct
1.52 +transfers at a tempo dictated by Timer3. Finally, DMA3 acts as the "reset" or
1.53 +"zero" channel to ensure that the pixel level is set to black at the end of
1.54 +each display line.
1.55 +
1.56 +In principle, other initiating conditions can be used instead of Timer3, which
1.57 +is configured to produce such conditions as frequently as possible:
1.58 +
1.59 + * A persistent interrupt condition can be employed instead. For example,
1.60 + configuring UART2 and setting the UART2 transfer interrupt, employing this
1.61 + interrupt condition for DMA0 and DMA2, produces the same effect.
1.62 +
1.63 + * An external interrupt such as INT2 can be configured, and the peripheral
1.64 + clock can be routed through the CLKO pin and back into the microcontroller
1.65 + via an appropriate pin. With INT2 being employed as the interrupt
1.66 + condition for DMA0 and DMA2, the same effect is produced.
1.67 +
1.68 +== Hardware Details ==
1.69 +
1.70 +The pin usage of this solution is documented below.
1.71 +
1.72 +=== PIC32MX270F256B-50I/SP Pin Assignments ===
1.73 +
1.74 +{{{
1.75 +MCLR# 1 \/ 28
1.76 +HSYNC/OC1/RA0 2 27
1.77 +VSYNC/OC2/RA1 3 26 RB15/U1TX
1.78 + D0/RB0 4 25 RB14
1.79 + D1/RB1 5 24 RB13/U1RX
1.80 + D2/RB2 6 23
1.81 + D3/RB3 7 22 RB11/PGEC2
1.82 + 8 21 RB10/PGEC3
1.83 + RA2 9 20
1.84 + RA3 10 19
1.85 + D4/RB4 11 18 RB9
1.86 + 12 17 RB8
1.87 + 13 16 RB7/D7
1.88 + D5/RB5 14 15
1.89 +}}}
1.90 +
1.91 +Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
1.92 +unlike the MX170 variant).
1.93 +
1.94 +=== UART Connections ===
1.95 +
1.96 +UART1 is exposed by the RB13 and RB15 pins.
1.97 +
1.98 +=== Data Signal Routing ===
1.99 +
1.100 +For one bit of intensity, two bits per colour channel:
1.101 +
1.102 +{{{
1.103 +D7 -> 2200R -> I
1.104 +
1.105 +I -> diode -> R
1.106 +I -> diode -> G
1.107 +I -> diode -> B
1.108 +
1.109 +D6 (not connected)
1.110 +
1.111 +D5 -> 470R -> R
1.112 +D4 -> 1000R -> R
1.113 +D3 -> 470R -> G
1.114 +D2 -> 1000R -> G
1.115 +D1 -> 470R -> B
1.116 +D0 -> 1000R -> B
1.117 +
1.118 +HSYNC -> HS
1.119 +VSYNC -> VS
1.120 +}}}
1.121 +
1.122 +=== Output Socket Pinout ===
1.123 +
1.124 +{{{
1.125 +5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R)
1.126 +
1.127 + 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND)
1.128 +
1.129 +15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC)
1.130 +}}}
1.131 +
1.132 +=== Output Cable Pinout ===
1.133 +
1.134 +{{{
1.135 + 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND)
1.136 +
1.137 +6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND)
1.138 +
1.139 + 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC)
1.140 +}}}
1.141 +
1.142 +== References ==
1.143 +
1.144 +https://en.wikipedia.org/wiki/VGA_connector
1.145 +
1.146 +http://papilio.cc/index.php?n=Papilio.VGAWing
1.147 +
1.148 +http://lucidscience.com/pro-vga%20video%20generator-2.aspx
1.149 +
1.150 +https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga