1.1 --- a/examples/vga-dual/README.txt Thu May 02 23:21:32 2019 +0200
1.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
1.3 @@ -1,109 +0,0 @@
1.4 -Introduction
1.5 -------------
1.6 -
1.7 -This example demonstrates the generation of an analogue VGA signal from a
1.8 -PIC32 microcontroller using general output pins. It follows on from the work
1.9 -done in the VGAPIC32 project. The result is not entirely satisfactory:
1.10 -
1.11 - * Every fourth pixel is wider than the others, this apparently being an
1.12 - artefact of the DMA transfer mechanism.
1.13 -
1.14 -It might be possible to introduce some kind of delay and even out the pixel
1.15 -widths, but this has not been investigated with hardware. However, unlike the
1.16 -vga-pmp example, there is no accompanying signal to potentially orchestrate
1.17 -the staging of individual pixels at a slightly delayed rate. Potentially, the
1.18 -peripheral clock signal might be generated and processed to make such a
1.19 -signal.
1.20 -
1.21 -Unlike the vga example, this example employs two DMA channels for pixel data
1.22 -which are interleaved to investigate a potential remedy for the wide pixel
1.23 -effect. Unfortunately, despite each channel contributing every other word (or
1.24 -group of four pixels), the effect persists. However, the picture is perhaps
1.25 -more stable than in the vga example.
1.26 -
1.27 -One significant problem with this example is that scrolling causes the DMA
1.28 -channels to become ordered incorrectly. This does not affect the vga-timer
1.29 -example which also employs two DMA channels.
1.30 -
1.31 -Hardware Details
1.32 -================
1.33 -
1.34 -The pin usage of this solution is documented below.
1.35 -
1.36 -PIC32MX270F256B-50I/SP Pin Assignments
1.37 ---------------------------------------
1.38 -
1.39 -MCLR# 1 \/ 28
1.40 -HSYNC/OC1/RA0 2 27
1.41 -VSYNC/OC2/RA1 3 26 RB15/U1TX
1.42 - D0/RB0 4 25 RB14
1.43 - D1/RB1 5 24 RB13/U1RX
1.44 - D2/RB2 6 23
1.45 - D3/RB3 7 22 RB11/PGEC2
1.46 - 8 21 RB10/PGEC3
1.47 - RA2 9 20
1.48 - RA3 10 19
1.49 - D4/RB4 11 18 RB9
1.50 - 12 17 RB8
1.51 - 13 16 RB7/D7
1.52 - D5/RB5 14 15
1.53 -
1.54 -Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
1.55 -unlike the MX170 variant).
1.56 -
1.57 -UART Connections
1.58 -----------------
1.59 -
1.60 -UART1 is exposed by the RB13 and RB15 pins.
1.61 -
1.62 -Data Signal Routing
1.63 --------------------
1.64 -
1.65 -For one bit of intensity, two bits per colour channel:
1.66 -
1.67 -D7 -> 2200R -> I
1.68 -
1.69 -I -> diode -> R
1.70 -I -> diode -> G
1.71 -I -> diode -> B
1.72 -
1.73 -D6 (not connected)
1.74 -
1.75 -D5 -> 470R -> R
1.76 -D4 -> 1000R -> R
1.77 -D3 -> 470R -> G
1.78 -D2 -> 1000R -> G
1.79 -D1 -> 470R -> B
1.80 -D0 -> 1000R -> B
1.81 -
1.82 -HSYNC -> HS
1.83 -VSYNC -> VS
1.84 -
1.85 -Output Socket Pinout
1.86 ---------------------
1.87 -
1.88 - 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R)
1.89 -
1.90 - 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND)
1.91 -
1.92 - 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC)
1.93 -
1.94 -Output Cable Pinout
1.95 --------------------
1.96 -
1.97 - 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND)
1.98 -
1.99 - 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND)
1.100 -
1.101 - 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC)
1.102 -
1.103 -References
1.104 -----------
1.105 -
1.106 -https://en.wikipedia.org/wiki/VGA_connector
1.107 -
1.108 -http://papilio.cc/index.php?n=Papilio.VGAWing
1.109 -
1.110 -http://lucidscience.com/pro-vga%20video%20generator-2.aspx
1.111 -
1.112 -https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga