1.1 --- a/examples/vga-pmp/README.txt Thu May 02 23:21:32 2019 +0200
1.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
1.3 @@ -1,111 +0,0 @@
1.4 -Introduction
1.5 -------------
1.6 -
1.7 -This example demonstrates the generation of an analogue VGA signal from a
1.8 -PIC32 microcontroller using the parallel mode (parallel master port, PMP)
1.9 -peripheral. The result is not entirely satisfactory:
1.10 -
1.11 - * Pixels are very narrow unless buffered using a flip-flop driven by the
1.12 - peripheral, this being a characteristic of the way the peripheral works, it
1.13 - normally being used to drive memory and display controllers.
1.14 -
1.15 - * Introducing a flip-flop means that the final pixel from the pixel data
1.16 - remains asserted and must be reset using a second DMA channel.
1.17 -
1.18 - * Every fourth pixel is wider than the others, this apparently being an
1.19 - artefact of the DMA transfer mechanism.
1.20 -
1.21 -It might be possible introduce some kind of delay to the write strobe (PMWR)
1.22 -and even out the pixel widths, but this has not been investigated.
1.23 -
1.24 -It appears to be the case that the system and peripheral clock frequencies
1.25 -need to be matched. In this example, a frequency of 48MHz has been chosen.
1.26 -
1.27 -Hardware Details
1.28 -================
1.29 -
1.30 -The pin usage of this solution is documented below.
1.31 -
1.32 -PIC32MX270F256B-50I/SP Pin Assignments
1.33 ---------------------------------------
1.34 -
1.35 -MCLR# 1 \/ 28
1.36 - D7/PMD7/RA0 2 27
1.37 - D6/PMD6/RA1 3 26 RB15/U1TX
1.38 - D0/PMD0/RB0 4 25 RB14
1.39 - D1/PMD1/RB1 5 24 RB13/(PMRD)/U1RX
1.40 - D2/PMD2/RB2 6 23
1.41 - PMWR/RB3 7 22 RB11/PGEC2
1.42 - 8 21 RB10/PGEC3
1.43 - RA2 9 20
1.44 - (PMA0)/RA3 10 19
1.45 -HSYNC/OC1/RB4 11 18 RB9/PMD3/D3
1.46 - 12 17 RB8/PMD4/D4
1.47 - 13 16 RB7/PMD5/D5
1.48 -VSYNC/OC2/RB5 14 15
1.49 -
1.50 -Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
1.51 -unlike the MX170 variant).
1.52 -
1.53 -UART Connections
1.54 -----------------
1.55 -
1.56 -UART1 is exposed by the RB13 and RB15 pins.
1.57 -
1.58 -Data Signal Routing
1.59 --------------------
1.60 -
1.61 -A flip-flop is used to buffer the outputs:
1.62 -
1.63 -Dn -> 74HC273:Dn
1.64 - 74HC273:Qn -> Qn
1.65 -VCC -> 74HC273:MR#
1.66 -PMWR -> 74HC273:CP
1.67 -
1.68 -For two bits of intensity, two bits per colour channel:
1.69 -
1.70 -Q7 -> 2200R -> I
1.71 -Q6 -> 4700R -> I
1.72 -
1.73 -I -> diode -> R
1.74 -I -> diode -> G
1.75 -I -> diode -> B
1.76 -
1.77 -Q5 -> 470R -> R
1.78 -Q4 -> 1000R -> R
1.79 -Q3 -> 470R -> G
1.80 -Q2 -> 1000R -> G
1.81 -Q1 -> 470R -> B
1.82 -Q0 -> 1000R -> B
1.83 -
1.84 -HSYNC -> HS
1.85 -VSYNC -> VS
1.86 -
1.87 -Output Socket Pinout
1.88 ---------------------
1.89 -
1.90 - 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R)
1.91 -
1.92 - 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND)
1.93 -
1.94 - 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC)
1.95 -
1.96 -Output Cable Pinout
1.97 --------------------
1.98 -
1.99 - 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND)
1.100 -
1.101 - 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND)
1.102 -
1.103 - 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC)
1.104 -
1.105 -References
1.106 -----------
1.107 -
1.108 -https://en.wikipedia.org/wiki/VGA_connector
1.109 -
1.110 -http://papilio.cc/index.php?n=Papilio.VGAWing
1.111 -
1.112 -http://lucidscience.com/pro-vga%20video%20generator-2.aspx
1.113 -
1.114 -https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga