1 /* 2 * PIC32 microcontroller initialisation code. 3 * 4 * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 3 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "mips.h" 21 #include "pic32.h" 22 23 /* Disable JTAG functionality on pins. */ 24 25 .section .devcfg0, "a" 26 .word 0xfffffffb /* DEVCFG0<2> = JTAGEN = 0 */ 27 28 /* 29 Set the oscillator to be the FRC oscillator with PLL, with peripheral clock 30 divided by 2, and FRCDIV+PLL selected. 31 32 The watchdog timer (FWDTEN) is also disabled. 33 34 The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with 35 RPB4. 36 */ 37 38 .section .devcfg1, "a" 39 .word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1; 40 DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */ 41 42 /* 43 Set the FRC oscillator PLL function with an input division of 4, an output 44 division of 2, a multiplication of 24, yielding a multiplication of 3. 45 46 The FRC is apparently at 16MHz and this produces a system clock of 48MHz. 47 */ 48 49 .section .devcfg2, "a" 50 .word 0xfff9fffb /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001; 51 DEVCFG2<6:4> = FPLLMUL<2:0> = 111; 52 DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */ 53 54 /* The start routine is placed at the boot location. */ 55 56 .section .boot, "a" 57 58 .globl _start 59 .extern main 60 61 _start: 62 /* Enable caching. */ 63 64 mfc0 $v1, CP0_CONFIG 65 li $t8, ~CONFIG_K0 66 and $v1, $v1, $t8 67 ori $v1, $v1, CONFIG_K0_CACHABLE_NONCOHERENT 68 mtc0 $v1, CP0_CONFIG 69 nop 70 71 /* Get the RAM size. */ 72 73 la $v1, BMXDRMSZ 74 lw $t0, 0($v1) 75 76 /* Initialise the stack pointer. */ 77 78 li $v1, KSEG0_BASE 79 addu $sp, $t0, $v1 /* sp = KSEG0_BASE + RAM size */ 80 81 /* Initialise the globals pointer. */ 82 83 lui $gp, %hi(_GLOBAL_OFFSET_TABLE_) 84 ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_) 85 86 /* 87 Jump to the main program. Since the boot code is separate from the 88 other code, the address cannot be obtained via the GOT. 89 ("relocation truncated to fit: R_MIPS_PC16 against `main'") 90 */ 91 92 lui $t9, %hi(main) 93 ori $t9, $t9, %lo(main) 94 jr $t9 95 nop