/*  * PIC32 peripheral descriptions.  *  * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk>  *  * This program is free software: you can redistribute it and/or modify  * it under the terms of the GNU General Public License as published by  * the Free Software Foundation, either version 3 of the License, or  * (at your option) any later version.  *  * This program is distributed in the hope that it will be useful,  * but WITHOUT ANY WARRANTY; without even the implied warranty of  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the  * GNU General Public License for more details.  *  * You should have received a copy of the GNU General Public License  * along with this program.  If not, see <http://www.gnu.org/licenses/>.  */  #ifndef __PIC32_H__ #define __PIC32_H__  /* Peripheral addresses.  * See...  * TABLE 4-1: SFR MEMORYMAP  * TABLE 11-3: PORTA REGISTER MAP  * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet  */  #define OSCCON          0xBF80F000 #define REFOCON         0xBF80F020 #define REFOTRIM        0xBF80F030 #define CFGCON          0xBF80F200 #define SYSKEY          0xBF80F230  #define INT2R           0xBF80FA08 #define U1RXR           0xBF80FA50  #define RPA0R           0xBF80FB00 #define RPA1R           0xBF80FB04 #define RPA2R           0xBF80FB08 #define RPA3R           0xBF80FB0C #define RPA4R           0xBF80FB10 #define RPB0R           0xBF80FB2C #define RPB1R           0xBF80FB30 #define RPB2R           0xBF80FB34 #define RPB3R           0xBF80FB38 #define RPB4R           0xBF80FB3C #define RPB5R           0xBF80FB40 #define RPB10R          0xBF80FB54 #define RPB15R          0xBF80FB68  #define INTCON          0xBF881000 #define IFS0            0xBF881030 #define IFS1            0xBF881040 #define IEC0            0xBF881060 #define IEC1            0xBF881070 #define IPC0            0xBF881090 #define IPC1            0xBF8810A0 #define IPC2            0xBF8810B0 #define IPC3            0xBF8810C0 #define IPC4            0xBF8810D0 #define IPC5            0xBF8810E0 #define IPC6            0xBF8810F0 #define IPC7            0xBF881100 #define IPC8            0xBF881110 #define IPC9            0xBF881120 #define IPC10           0xBF881130  #define BMXCON          0xBF882000 #define BMXDKPBA        0xBF882010 #define BMXDUDBA        0xBF882020 #define BMXDUPBA        0xBF882030 #define BMXDRMSZ        0xBF882040  #define ANSELA          0xBF886000 #define TRISA           0xBF886010 #define PORTA           0xBF886020 #define LATA            0xBF886030 #define ODCA            0xBF886040 #define ANSELB          0xBF886100 #define TRISB           0xBF886110 #define PORTB           0xBF886120 #define LATB            0xBF886130 #define ODCB            0xBF886140  /* DEVCFG conveniences. */  #define DEVCFG1_UNUSED              0xff7fcbd8 /* exclude FWDTWINSZ, WINDIS, WDTPS, FCKSM, POSCMOD, IESO */  #define DEVCFG1_FWDTEN_OFF          (0 << 23) #define DEVCFG1_FWDTEN_ON           (1 << 23)  #define DEVCFG1_FPBDIV_1            (0b00 << 12) #define DEVCFG1_FPBDIV_2            (0b01 << 12) #define DEVCFG1_FPBDIV_4            (0b10 << 12) #define DEVCFG1_FPBDIV_8            (0b11 << 12)  #define DEVCFG1_OSCIOFNC_ON         (0 << 10) #define DEVCFG1_OSCIOFNC_OFF        (1 << 10)  #define DEVCFG1_FSOSCEN_OFF         (0 << 5) #define DEVCFG1_FSOSCEN_ON          (1 << 5)  #define DEVCFG1_FNOSC_FRC           (0b000) #define DEVCFG1_FNOSC_FRCDIV_PLL    (0b001) #define DEVCFG1_FNOSC_FRCDIV        (0b111)  #define DEVCFG2_UNUSED              0xfff8ff88 /* exclude UPLLEN, UPLLIDIV */  #define DEVCFG2_FPLLODIV_1          (0b000 << 16) #define DEVCFG2_FPLLODIV_2          (0b001 << 16) #define DEVCFG2_FPLLODIV_4          (0b010 << 16) #define DEVCFG2_FPLLODIV_8          (0b011 << 16) #define DEVCFG2_FPLLODIV_16         (0b100 << 16) #define DEVCFG2_FPLLODIV_32         (0b101 << 16) #define DEVCFG2_FPLLODIV_64         (0b110 << 16) #define DEVCFG2_FPLLODIV_128        (0b111 << 16)  #define DEVCFG2_FPLLMUL_15          (0b000 << 4) #define DEVCFG2_FPLLMUL_16          (0b001 << 4) #define DEVCFG2_FPLLMUL_17          (0b010 << 4) #define DEVCFG2_FPLLMUL_18          (0b011 << 4) #define DEVCFG2_FPLLMUL_19          (0b100 << 4) #define DEVCFG2_FPLLMUL_20          (0b101 << 4) #define DEVCFG2_FPLLMUL_21          (0b110 << 4) #define DEVCFG2_FPLLMUL_24          (0b111 << 4)  #define DEVCFG2_FPLLIDIV_1          (0b000) #define DEVCFG2_FPLLIDIV_2          (0b001) #define DEVCFG2_FPLLIDIV_3          (0b010) #define DEVCFG2_FPLLIDIV_4          (0b011) #define DEVCFG2_FPLLIDIV_5          (0b100) #define DEVCFG2_FPLLIDIV_6          (0b101) #define DEVCFG2_FPLLIDIV_10         (0b110) #define DEVCFG2_FPLLIDIV_12         (0b111)  /* DMA conveniences. */  #define DMACON          0xBF883000 #define DCH0CON         0xBF883060 #define DCH1CON         0xBF883120 #define DCH2CON         0xBF8831E0 #define DCH3CON         0xBF8832A0  #define DCHMIN          0 #define DCHMAX          3 #define DCHBASE         DCH0CON #define DCHSTEP         (DCH1CON - DCH0CON)  #define DCHxCON         0x00 #define DCHxECON        0x10 #define DCHxINT         0x20 #define DCHxSSA         0x30 #define DCHxDSA         0x40 #define DCHxSSIZ        0x50 #define DCHxDSIZ        0x60 #define DCHxSPTR        0x70 #define DCHxDPTR        0x80 #define DCHxCSIZ        0x90 #define DCHxCPTR        0xA0 #define DCHxDAT         0xB0  #define DMAIEC          IEC1  #define DCHxIE          1  #define DMAIFS          IFS1  #define DCHxIF          1  #define DMAINTBASE      28  #define DMAIPC          IPC10 #define DCHIPCBASE      0 #define DCHIPCSTEP      8  /* External interrupt conveniences. */  #define INTMIN          0 #define INTMAX          4  #define INTIEC          IEC0  #define INTxIE          1  #define INTIFS          IFS0  #define INTxIF          1  #define INTINTBASE      3 #define INTINTSTEP      5  #define INT0IPC         IPC0 #define INT1IPC         IPC1 #define INT2IPC         IPC2 #define INT3IPC         IPC3 #define INT4IPC         IPC4 #define INTIPCBASE      24  /* Output compare conveniences. */  #define OC1CON          0xBF803000 #define OC2CON          0xBF803200 #define OC3CON          0xBF803400 #define OC4CON          0xBF803600 #define OC5CON          0xBF803800  #define OCMIN           1 #define OCMAX           5 #define OCBASE          OC1CON #define OCSTEP          (OC2CON - OC1CON)  #define OCxCON          0x00 #define OCxR            0x10 #define OCxRS           0x20  #define OCIEC           IEC0  #define OCxIE           1  #define OCIFS           IFS0  #define OCxIF           1  #define OCINTBASE       7 #define OCINTSTEP       5  #define OC1IPC          IPC1 #define OC2IPC          IPC2 #define OC3IPC          IPC3 #define OC4IPC          IPC4 #define OC5IPC          IPC5 #define OCIPCBASE       16  /* Parallel mode conveniences. */  #define PMCON           0xBF807000  #define PMxCON          0x00 #define PMxMODE         0x10 #define PMxADDR         0x20 #define PMxDOUT         0x30 #define PMxDIN          0x40 #define PMxAEN          0x50 #define PMxSTAT         0x60  #define PMMIN           0 #define PMMAX           0 #define PMBASE          PMCON #define PMSTEP          0  #define PMIEC           IEC1  #define PMxIE           1 #define PMxEIE          2  #define PMIFS           IFS1  #define PMxIF           1 #define PMxEIF          2  #define PMINTBASE       16 #define PMINTSTEP       0  #define PMIPC           IPC8 #define PMIPCBASE       24  /* Timer conveniences. */  #define T1CON           0xBF800600 #define T2CON           0xBF800800 #define T3CON           0xBF800A00 #define T4CON           0xBF800C00 #define T5CON           0xBF800E00  #define TIMERMIN        1 #define TIMERMAX        5 #define TIMERBASE       T1CON #define TIMERSTEP       (T2CON - T1CON)  #define TxCON           0x00 #define TMRx            0x10 #define PRx             0x20  #define TIMERIEC        IEC0  #define TxIE            1  #define TIMERIFS        IEC0  #define TxIF            1  #define TIMERINTBASE    4 #define TIMERINTSTEP    5  #define TIMER1IPC       IPC1 #define TIMER2IPC       IPC2 #define TIMER3IPC       IPC3 #define TIMER4IPC       IPC4 #define TIMER5IPC       IPC5 #define TIMERIPCBASE    0  /* UART conveniences. */  #define U1MODE          0xBF806000 #define U2MODE          0xBF806200  #define UARTMIN         1 #define UARTMAX         2 #define UARTBASE        U1MODE #define UARTSTEP        (U2MODE - U1MODE)  #define UxMODE          0x00 #define UxSTA           0x10 #define UxTXREG         0x20 #define UxRXREG         0x30 #define UxBRG           0x40  #define UARTIEC         IEC1  #define UxEIE           1 #define UxRIE           2 #define UxTIE           4  #define UARTIFS         IFS1  #define UxEIF           1 #define UxRIF           2 #define UxTIF           4  #define UARTINTBASE     7 #define UARTINTSTEP     14  #define UART1IPC        IPC8 #define UART1IPCBASE    0 #define UART2IPC        IPC9 #define UART2IPCBASE    8  /* Interrupt numbers.  * See...  * TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION  * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet  */  #define DMA0            60 #define DMA1            61 #define DMA2            62 #define DMA3            63 #define INT0            3 #define INT1            8 #define INT2            13 #define INT3            18 #define INT4            23 #define OC1             7 #define OC2             12 #define OC3             17 #define OC4             22 #define OC5             27 #define PMP             48 #define PMPE            49 #define T1              4 #define T2              9 #define T3              14 #define T4              19 #define T5              24 #define U1RX            40 #define U1TX            41 #define U2RX            54 #define U2TX            55  /* Address modifiers.  * See...  * 11.2 CLR, SET and INV Registers  * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet  */  #define CLR             0x4 #define SET             0x8 #define INV             0xC  #endif /* __PIC32_H__ */