1 /* 2 * PIC32 peripheral configuration and initialisation. 3 * 4 * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 3 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "cpu.h" 21 #include "pic32_c.h" 22 #include "init.h" 23 24 25 26 /* Basic memory and pin initialisation. */ 27 28 void init_memory(void) 29 { 30 /* 31 Configure RAM. 32 See: http://microchipdeveloper.com/32bit:mx-arch-exceptions-processor-initialization 33 */ 34 35 uint32_t config = REG(BMXCON); 36 37 /* Set zero wait states for address setup. */ 38 39 config &= ~(1 << 6); /* BMXCON<6> = BMXWSDRM = 0 */ 40 41 /* Set bus arbitration mode. */ 42 43 config &= ~0b111; 44 config |= 0b010; /* BMXCON<2:0> = BMXARB<2:0> = 2 */ 45 46 REG(BMXCON) = config; 47 } 48 49 void init_pins(void) 50 { 51 /* DEVCFG0<2> also needs setting to 0 before the program is run. */ 52 53 CLR_REG(CFGCON, 1 << 3); /* CFGCON<3> = JTAGEN = 0 */ 54 } 55 56 void init_outputs(void) 57 { 58 /* Remove analogue features from pins. */ 59 60 REG(ANSELA) = 0; 61 REG(ANSELB) = 0; 62 63 /* Set pins as outputs. */ 64 65 REG(TRISA) = 0; 66 REG(TRISB) = 0; 67 68 /* Clear outputs. */ 69 70 REG(PORTA) = 0; 71 REG(PORTB) = 0; 72 } 73 74 75 76 /* Peripheral pin configuration. */ 77 78 void lock_config(void) 79 { 80 SET_REG(CFGCON, 1 << 13); /* IOLOCK = 1 */ 81 82 /* Lock the configuration again. */ 83 84 REG(SYSKEY) = 0x33333333; 85 } 86 87 void unlock_config(void) 88 { 89 /* Unlock the configuration register bits. */ 90 91 REG(SYSKEY) = 0; 92 REG(SYSKEY) = 0xAA996655; 93 REG(SYSKEY) = 0x556699AA; 94 95 CLR_REG(CFGCON, 1 << 13); /* IOLOCK = 0 */ 96 } 97 98 99 100 /* Convenience operations. */ 101 102 void interrupts_on(void) 103 { 104 init_interrupts(); 105 enable_interrupts(); 106 handle_error_level(); 107 } 108 109 110 111 /* DMA configuration. */ 112 113 void init_dma(void) 114 { 115 /* Disable DMA interrupts (DMAxIE). */ 116 117 CLR_REG(DMAIEC, 0b1111 << DMAINTBASE); 118 119 /* Clear DMA interrupt flags (DMAxIF). */ 120 121 CLR_REG(DMAIFS, 0b1111 << DMAINTBASE); 122 123 /* Enable DMA. */ 124 125 SET_REG(DMACON, 1 << 15); 126 } 127 128 /* Initialise the given channel. */ 129 130 void dma_init(int channel, uint8_t pri) 131 { 132 if ((channel < DCHMIN) || (channel > DCHMAX)) 133 return; 134 135 /* Initialise a channel. */ 136 137 REG(DMA_REG(channel, DCHxCON)) = pri & 0b11; 138 REG(DMA_REG(channel, DCHxECON)) = 0; 139 REG(DMA_REG(channel, DCHxINT)) = 0; 140 } 141 142 /* Set the channel repeated enable mode, enabling it again when a block transfer 143 completes. The documentation describes this as auto-enable. */ 144 145 void dma_set_auto_enable(int channel, int enable) 146 { 147 (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 4); 148 } 149 150 /* Set the channel chaining mode. */ 151 152 void dma_set_chaining(int channel, enum dma_chain chain) 153 { 154 (chain != dma_chain_none ? 155 SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 5); 156 157 (chain == dma_chain_next ? 158 SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 8); 159 } 160 161 /* Configure a channel's initiation interrupt. */ 162 163 void dma_set_interrupt(int channel, uint8_t int_num, int enable) 164 { 165 if ((channel < DCHMIN) || (channel > DCHMAX)) 166 return; 167 168 /* Allow an interrupt to trigger the transfer. */ 169 170 REG(DMA_REG(channel, DCHxECON)) = (int_num << 8) | 171 ((enable ? 1 : 0) << 4); 172 } 173 174 /* Configure only the channel's initiation interrupt status. */ 175 176 void dma_set_interrupt_enable(int channel, int enable) 177 { 178 if ((channel < DCHMIN) || (channel > DCHMAX)) 179 return; 180 181 (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxECON), 1 << 4); 182 } 183 184 /* Permit the channel to register events while disabled or suspended. A 185 suspended channel is one that is enabled but where the DMA peripheral 186 has been suspended. */ 187 188 void dma_set_receive_events(int channel, int enable) 189 { 190 (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 6); 191 } 192 193 /* Set a channel's transfer parameters. */ 194 195 void dma_set_transfer(int channel, 196 uint32_t source_start_address, uint16_t source_size, 197 uint32_t destination_start_address, uint16_t destination_size, 198 uint16_t cell_size) 199 { 200 if ((channel < DCHMIN) || (channel > DCHMAX)) 201 return; 202 203 REG(DMA_REG(channel, DCHxSSIZ)) = source_size; 204 REG(DMA_REG(channel, DCHxSSA)) = source_start_address; 205 REG(DMA_REG(channel, DCHxDSIZ)) = destination_size; 206 REG(DMA_REG(channel, DCHxDSA)) = destination_start_address; 207 REG(DMA_REG(channel, DCHxCSIZ)) = cell_size; 208 } 209 210 /* Configure interrupts caused by the channel. */ 211 212 void dma_init_interrupt(int channel, uint8_t conditions, 213 uint8_t pri, uint8_t sub) 214 { 215 if ((channel < DCHMIN) || (channel > DCHMAX)) 216 return; 217 218 /* Disable channel interrupt and clear interrupt flag. */ 219 220 CLR_REG(DMAIEC, DMA_INT_FLAGS(channel, 1)); 221 CLR_REG(DMAIFS, DMA_INT_FLAGS(channel, 1)); 222 223 /* Produce an interrupt for the provided conditions. */ 224 225 REG(DMA_REG(channel, DCHxINT)) = conditions << 16; 226 227 /* Set interrupt priorities. */ 228 229 REG(DMAIPC) = (REG(DMAIPC) & 230 ~(DMA_IPC_PRI(channel, 7, 3))) | 231 DMA_IPC_PRI(channel, pri, sub); 232 233 /* Enable interrupt. */ 234 235 SET_REG(DMAIEC, DMA_INT_FLAGS(channel, 1)); 236 } 237 238 /* Enable or disable the channel. */ 239 240 void dma_set_enable(int channel, int enable) 241 { 242 if ((channel < DCHMIN) || (channel > DCHMAX)) 243 return; 244 245 (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 7); 246 } 247 248 /* Disable a DMA channel. */ 249 250 void dma_off(int channel) 251 { 252 dma_set_enable(channel, 0); 253 } 254 255 /* Enable a DMA channel. */ 256 257 void dma_on(int channel) 258 { 259 dma_set_enable(channel, 1); 260 } 261 262 263 264 /* External interrupt initialisation. */ 265 266 void int_init_interrupt(int int_num, uint8_t pri, uint8_t sub) 267 { 268 if ((int_num < INTMIN) || (int_num > INTMAX)) 269 return; 270 271 /* Disable interrupt and clear interrupt flag. */ 272 273 CLR_REG(INTIEC, INT_INT_FLAGS(int_num, INTxIE)); 274 CLR_REG(INTIFS, INT_INT_FLAGS(int_num, INTxIF)); 275 276 /* Set interrupt priorities. */ 277 278 REG(INT_IPC_REG(int_num)) = (REG(INT_IPC_REG(int_num)) & 279 ~(INT_IPC_PRI(int_num, 7, 3))) | 280 INT_IPC_PRI(int_num, pri, sub); 281 282 /* Enable interrupt. */ 283 284 SET_REG(INTIEC, INT_INT_FLAGS(int_num, INTxIE)); 285 } 286 287 288 289 /* Output compare configuration. */ 290 291 void oc_init(int unit, uint8_t mode, int timer) 292 { 293 if ((unit < OCMIN) || (unit > OCMAX)) 294 return; 295 296 REG(OC_REG(unit, OCxCON)) = (timer == 3 ? (1 << 3) : 0) | (mode & 0b111); 297 } 298 299 /* Set the start value for the pulse. */ 300 301 void oc_set_pulse(int unit, uint32_t start) 302 { 303 if ((unit < OCMIN) || (unit > OCMAX)) 304 return; 305 306 REG(OC_REG(unit, OCxR)) = start; 307 } 308 309 /* Set the end value for the pulse. */ 310 311 void oc_set_pulse_end(int unit, uint32_t end) 312 { 313 if ((unit < OCMIN) || (unit > OCMAX)) 314 return; 315 316 REG(OC_REG(unit, OCxRS)) = end; 317 } 318 319 /* Configure interrupts caused by the unit. */ 320 321 void oc_init_interrupt(int unit, uint8_t pri, uint8_t sub) 322 { 323 if ((unit < OCMIN) || (unit > OCMAX)) 324 return; 325 326 /* Disable interrupt and clear interrupt flag. */ 327 328 CLR_REG(OCIEC, OC_INT_FLAGS(unit, OCxIE)); 329 CLR_REG(OCIFS, OC_INT_FLAGS(unit, OCxIF)); 330 331 /* Set interrupt priorities. */ 332 333 REG(OC_IPC_REG(unit)) = (REG(OC_IPC_REG(unit)) & 334 ~(OC_IPC_PRI(unit, 7, 3))) | 335 OC_IPC_PRI(unit, pri, sub); 336 337 /* Enable interrupt. */ 338 339 SET_REG(OCIEC, OC_INT_FLAGS(unit, OCxIE)); 340 } 341 342 /* Enable a unit. */ 343 344 void oc_on(int unit) 345 { 346 if ((unit < OCMIN) || (unit > OCMAX)) 347 return; 348 349 SET_REG(OC_REG(unit, OCxCON), 1 << 15); 350 } 351 352 353 354 /* Parallel mode configuration. */ 355 356 void init_pm(void) 357 { 358 int i; 359 360 /* Disable PM interrupts (PMxIE). */ 361 362 CLR_REG(PMIEC, 0b11 << PMINTBASE); 363 364 /* Clear PM interrupt flags (PMxIF). */ 365 366 CLR_REG(PMIFS, 0b11 << PMINTBASE); 367 368 /* Disable PM for configuration. */ 369 370 for (i = PMMIN; i <= PMMAX; i++) 371 REG(PM_REG(i, PMxCON)) = 0; 372 } 373 374 /* Configure the parallel mode. */ 375 376 void pm_init(int port, uint8_t mode) 377 { 378 if ((port < PMMIN) || (port > PMMAX)) 379 return; 380 381 REG(PM_REG(port, PMxMODE)) = (mode & 0b11) << 8; 382 REG(PM_REG(port, PMxAEN)) = 0; 383 REG(PM_REG(port, PMxADDR)) = 0; 384 } 385 386 /* Configure output signals. */ 387 388 void pm_set_output(int port, int write_enable, int read_enable) 389 { 390 if ((port < PMMIN) || (port > PMMAX)) 391 return; 392 393 REG(PM_REG(port, PMxCON)) = (write_enable ? (1 << 9) : 0) | 394 (read_enable ? (1 << 8) : 0) | 395 (1 << 1); /* WRSP: PMENB active high */ 396 } 397 398 /* Configure interrupts caused by parallel mode. */ 399 400 void pm_init_interrupt(int port, uint8_t pri, uint8_t sub) 401 { 402 if ((port < PMMIN) || (port > PMMAX)) 403 return; 404 405 /* Disable interrupt and clear interrupt flag. */ 406 407 CLR_REG(PMIEC, PM_INT_FLAGS(port, PMxIE)); 408 CLR_REG(PMIFS, PM_INT_FLAGS(port, PMxIF)); 409 410 /* Set interrupt priorities. */ 411 412 REG(PM_IPC_REG(port)) = (REG(PM_IPC_REG(port)) & 413 ~(PM_IPC_PRI(port, 7, 3))) | 414 PM_IPC_PRI(port, pri, sub); 415 416 /* Enable interrupt. */ 417 418 SET_REG(PMIEC, PM_INT_FLAGS(port, PMxIE)); 419 } 420 421 /* Enable parallel mode. */ 422 423 void pm_on(int port) 424 { 425 if ((port < PMMIN) || (port > PMMAX)) 426 return; 427 428 SET_REG(PM_REG(port, PMxCON), 1 << 15); 429 } 430 431 /* Disable parallel mode. */ 432 433 void pm_off(int port) 434 { 435 if ((port < PMMIN) || (port > PMMAX)) 436 return; 437 438 CLR_REG(PM_REG(port, PMxCON), 1 << 15); 439 } 440 441 442 443 444 /* Timer configuration. */ 445 446 void timer_init(int timer, uint8_t prescale, uint16_t limit) 447 { 448 /* NOTE: Should convert from the real prescale value. */ 449 450 REG(TIMER_REG(timer, TxCON)) = (prescale & 0b111) << 4; 451 REG(TIMER_REG(timer, TMRx)) = 0; 452 REG(TIMER_REG(timer, PRx)) = limit; 453 } 454 455 /* Configure interrupts caused by the timer. */ 456 457 void timer_init_interrupt(int timer, uint8_t pri, uint8_t sub) 458 { 459 if ((timer < TIMERMIN) || (timer > TIMERMAX)) 460 return; 461 462 /* Disable interrupt and clear interrupt flag. */ 463 464 CLR_REG(TIMERIEC, TIMER_INT_FLAGS(timer, TxIE)); 465 CLR_REG(TIMERIFS, TIMER_INT_FLAGS(timer, TxIF)); 466 467 /* Set interrupt priorities. */ 468 469 REG(TIMER_IPC_REG(timer)) = (REG(TIMER_IPC_REG(timer)) & 470 ~(TIMER_IPC_PRI(timer, 7, 3))) | 471 TIMER_IPC_PRI(timer, pri, sub); 472 473 /* Enable interrupt. */ 474 475 SET_REG(TIMERIEC, TIMER_INT_FLAGS(timer, TxIE)); 476 } 477 478 /* Enable a timer. */ 479 480 void timer_on(int timer) 481 { 482 if ((timer < TIMERMIN) || (timer > TIMERMAX)) 483 return; 484 485 SET_REG(TIMER_REG(timer, TxCON), 1 << 15); 486 } 487 488 489 490 /* UART configuration. */ 491 492 void uart_init(int uart, uint32_t baudrate) 493 { 494 /* NOTE: Configured in the initial payload. */ 495 496 uint32_t FPB = 24000000; 497 498 if ((uart < UARTMIN) || (uart > UARTMAX)) 499 return; 500 501 /* Disable the UART (ON). */ 502 503 CLR_REG(UART_REG(uart, UxMODE), 1 << 15); 504 505 /* Set the baud rate. For example: 506 507 UxBRG<15:0> = BRG 508 = (FPB / (16 * baudrate)) - 1 509 = (24000000 / (16 * 115200)) - 1 510 = 12 511 */ 512 513 REG(UART_REG(uart, UxBRG)) = (FPB / (16 * baudrate)) - 1; 514 } 515 516 /* Configure interrupts caused by the UART. */ 517 518 void uart_init_interrupt(int uart, uint8_t conditions, 519 uint8_t pri, uint8_t sub) 520 { 521 if ((uart < UARTMIN) || (uart > UARTMAX)) 522 return; 523 524 /* Disable interrupts and clear interrupt flags. */ 525 526 CLR_REG(UARTIEC, UART_INT_FLAGS(uart, UxTIE | UxRIE | UxEIE)); 527 CLR_REG(UARTIFS, UART_INT_FLAGS(uart, UxTIF | UxRIF | UxEIF)); 528 529 /* Set priorities: UxIP = pri; UxIS = sub */ 530 531 REG(UART_IPC_REG(uart)) = (REG(UART_IPC_REG(uart)) & 532 ~UART_IPC_PRI(uart, 7, 3)) | 533 UART_IPC_PRI(uart, pri, sub); 534 535 /* Enable interrupts. */ 536 537 SET_REG(UARTIEC, UART_INT_FLAGS(uart, conditions)); 538 } 539 540 /* Enable a UART. */ 541 542 void uart_on(int uart) 543 { 544 if ((uart < UARTMIN) || (uart > UARTMAX)) 545 return; 546 547 /* Enable receive (URXEN) and transmit (UTXEN). */ 548 549 SET_REG(UART_REG(uart, UxSTA), (1 << 12) | (1 << 10)); 550 551 /* Start UART. */ 552 553 SET_REG(UART_REG(uart, UxMODE), 1 << 15); 554 } 555 556 557 558 /* Utility functions. */ 559 560 /* Return encoded interrupt priorities. */ 561 562 static uint8_t PRI(uint8_t pri, uint8_t sub) 563 { 564 return ((pri & 0b111) << 2) | (sub & 0b11); 565 } 566 567 /* Return the DMA interrupt flags for combining with a register. */ 568 569 int DMA_INT_FLAGS(int channel, uint8_t flags) 570 { 571 return (flags & 0b1) << (DMAINTBASE + (channel - DCHMIN)); 572 } 573 574 /* Return encoded DMA interrupt priorities for combining with a register. */ 575 576 uint32_t DMA_IPC_PRI(int channel, uint8_t pri, uint8_t sub) 577 { 578 return PRI(pri, sub) << (DCHIPCBASE + (channel - DCHMIN) * DCHIPCSTEP); 579 } 580 581 /* Return encoded external interrupt priorities for combining with a register. */ 582 583 uint32_t INT_IPC_PRI(int int_num, uint8_t pri, uint8_t sub) 584 { 585 (void) int_num; 586 return PRI(pri, sub) << INTIPCBASE; 587 } 588 589 /* Return the external interrupt priorities register. */ 590 591 uint32_t INT_IPC_REG(int int_num) 592 { 593 switch (int_num) 594 { 595 case 0: return INT0IPC; 596 case 1: return INT1IPC; 597 case 2: return INT2IPC; 598 case 3: return INT3IPC; 599 case 4: return INT4IPC; 600 default: return 0; /* should not occur */ 601 } 602 } 603 604 /* Return the external interrupt flags for combining with a register. */ 605 606 int INT_INT_FLAGS(int int_num, uint8_t flags) 607 { 608 return (flags & 0b1) << (INTINTBASE + (int_num - INTMIN) * INTINTSTEP); 609 } 610 611 /* Return encoded output compare interrupt priorities for combining with a register. */ 612 613 uint32_t OC_IPC_PRI(int unit, uint8_t pri, uint8_t sub) 614 { 615 (void) unit; 616 return PRI(pri, sub) << OCIPCBASE; 617 } 618 619 /* Return the output compare interrupt priorities register. */ 620 621 uint32_t OC_IPC_REG(int unit) 622 { 623 switch (unit) 624 { 625 case 1: return OC1IPC; 626 case 2: return OC2IPC; 627 case 3: return OC3IPC; 628 case 4: return OC4IPC; 629 case 5: return OC5IPC; 630 default: return 0; /* should not occur */ 631 } 632 } 633 634 /* Return the output compare interrupt flags for combining with a register. */ 635 636 int OC_INT_FLAGS(int unit, uint8_t flags) 637 { 638 return (flags & 0b1) << (OCINTBASE + (unit - OCMIN) * OCINTSTEP); 639 } 640 641 /* Return encoded parallel mode interrupt priorities for combining with a register. */ 642 643 uint32_t PM_IPC_PRI(int port, uint8_t pri, uint8_t sub) 644 { 645 (void) port; 646 return PRI(pri, sub) << PMIPCBASE; 647 } 648 649 /* Return the parallel mode interrupt priorities register. */ 650 651 uint32_t PM_IPC_REG(int port) 652 { 653 (void) port; 654 return PMIPC; 655 } 656 657 /* Return the parallel mode interrupt flags for combining with a register. */ 658 659 int PM_INT_FLAGS(int port, uint8_t flags) 660 { 661 return (flags & 0b11) << (PMINTBASE + (port - PMMIN) * PMINTSTEP); 662 } 663 664 /* Return encoded timer interrupt priorities for combining with a register. */ 665 666 uint32_t TIMER_IPC_PRI(int timer, uint8_t pri, uint8_t sub) 667 { 668 (void) timer; 669 return PRI(pri, sub) << TIMERIPCBASE; 670 } 671 672 /* Return the timer interrupt priorities register. */ 673 674 uint32_t TIMER_IPC_REG(int timer) 675 { 676 switch (timer) 677 { 678 case 1: return TIMER1IPC; 679 case 2: return TIMER2IPC; 680 case 3: return TIMER3IPC; 681 case 4: return TIMER4IPC; 682 case 5: return TIMER5IPC; 683 default: return 0; /* should not occur */ 684 } 685 } 686 687 /* Return the timer interrupt flags for combining with a register. */ 688 689 int TIMER_INT_FLAGS(int timer, uint8_t flags) 690 { 691 return (flags & 0b1) << (TIMERINTBASE + (timer - TIMERMIN) * TIMERINTSTEP); 692 } 693 694 /* Return encoded UART interrupt priorities for combining with a register. */ 695 696 uint32_t UART_IPC_PRI(int uart, uint8_t pri, uint8_t sub) 697 { 698 return PRI(pri, sub) << (uart == 1 ? UART1IPCBASE : UART2IPCBASE); 699 } 700 701 /* Return the UART interrupt priorities register. */ 702 703 uint32_t UART_IPC_REG(int uart) 704 { 705 return uart == 1 ? UART1IPC : UART2IPC; 706 } 707 708 /* Return the UART interrupt flags for combining with a register. */ 709 710 int UART_INT_FLAGS(int uart, uint8_t flags) 711 { 712 return (flags & 0b111) << (UARTINTBASE + (uart - UARTMIN) * UARTINTSTEP); 713 }