1 Introduction
2 ------------
3
4 This example demonstrates the generation of an analogue VGA signal from a
5 PIC32 microcontroller using general output pins. Unlike the vga and vga-pmp
6 examples, it employs a regular interrupt condition to schedule single-byte
7 (single-pixel) DMA transfers instead of a single whole-line transfer.
8
9 The principal advantage of this method over the whole-line transfer method is
10 its production of pixels with consistent widths. The principal disadvantage is
11 the significant loss of horizontal resolution due to the latencies involved in
12 propagating interrupt conditions to the DMA controller and thereby initiating
13 each transfer.
14
15 Employing a peripheral clock that has half the frequency of the system clock
16 should ensure the stability of the picture, since the lower frequency may make
17 transfers easier to schedule. The peripheral clock should provide a more
18 forgiving deadline for each transfer, permitting late transfers to complete on
19 time.
20
21 Meanwhile, matching the system and peripheral clock frequencies appears to
22 leave the scheduling of transfers open to uncertainty, with transfers being
23 more readily delayed by other activity in the system, and with instability of
24 the picture being the result.
25
26 Unlike the vga example, but in common with the vga-dual example, this example
27 employs two DMA channels for pixel data which are interleaved to investigate a
28 potential remedy for the wide pixel effect. This seems to preserve consistent
29 pixel widths only with a transfer cell size of 1: other cell sizes suffer from
30 the wide pixel problem. Despite not offering the greater throughput of larger
31 cell sizes, merely employing dual channels increases throughput for a cell
32 size of 1, making the technique worth using.
33
34 In contrast to the vga and vga-pmp examples, a special DMA channel is employed
35 to initiate the pixel transfer process without actually transferring any pixel
36 data itself. The channel arrangement is as follows:
37
38 Transfer Initiator DMA Channel Transfer Activity
39 ------------------ ----------- -----------------
40 Timer2 DMA1 zerodata -> PORTB
41 Timer3 DMA0 linedata -> PORTB
42 Timer3 DMA2 linedata -> PORTB
43 Timer3 DMA3 zerodata -> PORTB
44
45 The real purpose of this channel (DMA1) is to capture the Timer2 interrupt
46 condition and to enable the following channels (DMA0, DMA2) through channel
47 chaining. Having been enabled, DMA0 and DMA2 are then able to conduct
48 transfers at a tempo dictated by Timer3. Finally, DMA3 acts as the "reset" or
49 "zero" channel to ensure that the pixel level is set to black at the end of
50 each display line.
51
52 In principle, other initiating conditions can be used instead of Timer3, which
53 is configured to produce such conditions as frequently as possible:
54
55 * A persistent interrupt condition can be employed instead. For example,
56 configuring UART2 and setting the UART2 transfer interrupt, employing this
57 interrupt condition for DMA0 and DMA2, produces the same effect.
58
59 * An external interrupt such as INT2 can be configured, and the peripheral
60 clock can be routed through the CLKO pin and back into the microcontroller
61 via an appropriate pin. With INT2 being employed as the interrupt
62 condition for DMA0 and DMA2, the same effect is produced.
63
64 Hardware Details
65 ================
66
67 The pin usage of this solution is documented below.
68
69 PIC32MX270F256B-50I/SP Pin Assignments
70 --------------------------------------
71
72 MCLR# 1 \/ 28
73 HSYNC/OC1/RA0 2 27
74 VSYNC/OC2/RA1 3 26 RB15/U1TX
75 D0/RB0 4 25 RB14
76 D1/RB1 5 24 RB13/U1RX
77 D2/RB2 6 23
78 D3/RB3 7 22 RB11/PGEC2
79 8 21 RB10/PGEC3
80 RA2 9 20
81 RA3 10 19
82 D4/RB4 11 18 RB9
83 12 17 RB8
84 13 16 RB7/D7
85 D5/RB5 14 15
86
87 Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
88 unlike the MX170 variant).
89
90 UART Connections
91 ----------------
92
93 UART1 is exposed by the RB13 and RB15 pins.
94
95 Data Signal Routing
96 -------------------
97
98 For one bit of intensity, two bits per colour channel:
99
100 D7 -> 2200R -> I
101
102 I -> diode -> R
103 I -> diode -> G
104 I -> diode -> B
105
106 D6 (not connected)
107
108 D5 -> 470R -> R
109 D4 -> 1000R -> R
110 D3 -> 470R -> G
111 D2 -> 1000R -> G
112 D1 -> 470R -> B
113 D0 -> 1000R -> B
114
115 HSYNC -> HS
116 VSYNC -> VS
117
118 Output Socket Pinout
119 --------------------
120
121 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R)
122
123 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND)
124
125 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC)
126
127 Output Cable Pinout
128 -------------------
129
130 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND)
131
132 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND)
133
134 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC)
135
136 References
137 ----------
138
139 https://en.wikipedia.org/wiki/VGA_connector
140
141 http://papilio.cc/index.php?n=Papilio.VGAWing
142
143 http://lucidscience.com/pro-vga%20video%20generator-2.aspx
144
145 https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga
