1 /* 2 * PIC32 peripheral descriptions. 3 * 4 * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 3 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __PIC32_H__ 21 #define __PIC32_H__ 22 23 /* Peripheral addresses. 24 * See... 25 * TABLE 4-1: SFR MEMORYMAP 26 * TABLE 11-3: PORTA REGISTER MAP 27 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet 28 */ 29 30 #define PMCON 0xBF807000 31 #define PMMODE 0xBF807010 32 #define PMADDR 0xBF807020 33 #define PMDOUT 0xBF807030 34 #define PMDIN 0xBF807040 35 #define PMAEN 0xBF807050 36 #define PMSTAT 0xBF807060 37 38 #define OSCCON 0xBF80F000 39 #define REFOCON 0xBF80F020 40 #define REFOTRIM 0xBF80F030 41 #define CFGCON 0xBF80F200 42 #define SYSKEY 0xBF80F230 43 44 #define U1RXR 0xBF80FA50 45 46 #define RPA0R 0xBF80FB00 47 #define RPA1R 0xBF80FB04 48 #define RPA2R 0xBF80FB08 49 #define RPA3R 0xBF80FB0C 50 #define RPA4R 0xBF80FB10 51 #define RPB0R 0xBF80FB2C 52 #define RPB1R 0xBF80FB30 53 #define RPB2R 0xBF80FB34 54 #define RPB3R 0xBF80FB38 55 #define RPB4R 0xBF80FB3C 56 #define RPB5R 0xBF80FB40 57 #define RPB10R 0xBF80FB54 58 #define RPB15R 0xBF80FB68 59 60 #define INTCON 0xBF881000 61 #define IFS0 0xBF881030 62 #define IFS1 0xBF881040 63 #define IEC0 0xBF881060 64 #define IEC1 0xBF881070 65 #define IPC1 0xBF8810A0 66 #define IPC2 0xBF8810B0 67 #define IPC3 0xBF8810C0 68 #define IPC4 0xBF8810D0 69 #define IPC5 0xBF8810E0 70 #define IPC6 0xBF8810F0 71 #define IPC7 0xBF881100 72 #define IPC8 0xBF881110 73 #define IPC9 0xBF881120 74 #define IPC10 0xBF881130 75 76 #define BMXCON 0xBF882000 77 #define BMXDKPBA 0xBF882010 78 #define BMXDUDBA 0xBF882020 79 #define BMXDUPBA 0xBF882030 80 #define BMXDRMSZ 0xBF882040 81 82 #define ANSELA 0xBF886000 83 #define TRISA 0xBF886010 84 #define PORTA 0xBF886020 85 #define LATA 0xBF886030 86 #define ODCA 0xBF886040 87 #define ANSELB 0xBF886100 88 #define TRISB 0xBF886110 89 #define PORTB 0xBF886120 90 #define LATB 0xBF886130 91 #define ODCB 0xBF886140 92 93 /* DMA conveniences. */ 94 95 #define DMACON 0xBF883000 96 #define DCH0CON 0xBF883060 97 #define DCH1CON 0xBF883120 98 #define DCH2CON 0xBF8831E0 99 #define DCH3CON 0xBF8832A0 100 101 #define DCHMIN 0 102 #define DCHMAX 3 103 #define DCHBASE DCH0CON 104 #define DCHSTEP (DCH1CON - DCH0CON) 105 106 #define DCHxCON 0x00 107 #define DCHxECON 0x10 108 #define DCHxINT 0x20 109 #define DCHxSSA 0x30 110 #define DCHxDSA 0x40 111 #define DCHxSSIZ 0x50 112 #define DCHxDSIZ 0x60 113 #define DCHxSPTR 0x70 114 #define DCHxDPTR 0x80 115 #define DCHxCSIZ 0x90 116 #define DCHxCPTR 0xA0 117 #define DCHxDAT 0xB0 118 119 #define DMAIEC IEC1 120 121 #define DCHxIE 1 122 123 #define DMAIFS IFS1 124 125 #define DCHxIF 1 126 127 #define DMAINTBASE 28 128 129 #define DMAIPC IPC10 130 #define DCHIPCBASE 0 131 #define DCHIPCSTEP 8 132 133 /* Output compare conveniences. */ 134 135 #define OC1CON 0xBF803000 136 #define OC2CON 0xBF803200 137 #define OC3CON 0xBF803400 138 #define OC4CON 0xBF803600 139 #define OC5CON 0xBF803800 140 141 #define OCMIN 1 142 #define OCMAX 5 143 #define OCBASE OC1CON 144 #define OCSTEP (OC2CON - OC1CON) 145 146 #define OCxCON 0x00 147 #define OCxR 0x10 148 #define OCxRS 0x20 149 150 #define OCIEC IEC0 151 152 #define OCxIE 1 153 154 #define OCIFS IFS0 155 156 #define OCxIF 1 157 158 #define OCINTBASE 7 159 #define OCINTSTEP 5 160 161 #define OC1IPC IPC1 162 #define OC2IPC IPC2 163 #define OC3IPC IPC3 164 #define OC4IPC IPC4 165 #define OC5IPC IPC5 166 #define OCIPCBASE 16 167 168 /* Timer conveniences. */ 169 170 #define T1CON 0xBF800600 171 #define T2CON 0xBF800800 172 #define T3CON 0xBF800A00 173 #define T4CON 0xBF800C00 174 #define T5CON 0xBF800E00 175 176 #define TIMERMIN 1 177 #define TIMERMAX 5 178 #define TIMERBASE T1CON 179 #define TIMERSTEP (T2CON - T1CON) 180 181 #define TxCON 0x00 182 #define TMRx 0x10 183 #define PRx 0x20 184 185 #define TIMERIEC IEC0 186 187 #define TxIE 1 188 189 #define TIMERIFS IEC0 190 191 #define TxIF 1 192 193 #define TIMERINTBASE 4 194 #define TIMERINTSTEP 5 195 196 #define TIMER1IPC IPC1 197 #define TIMER2IPC IPC2 198 #define TIMER3IPC IPC3 199 #define TIMER4IPC IPC4 200 #define TIMER5IPC IPC5 201 #define TIMERIPCBASE 0 202 203 /* UART conveniences. */ 204 205 #define U1MODE 0xBF806000 206 #define U2MODE 0xBF806200 207 208 #define UARTMIN 1 209 #define UARTMAX 2 210 #define UARTBASE U1MODE 211 #define UARTSTEP (U2MODE - U1MODE) 212 213 #define UxMODE 0x00 214 #define UxSTA 0x10 215 #define UxTXREG 0x20 216 #define UxRXREG 0x30 217 #define UxBRG 0x40 218 219 #define UARTIEC IEC1 220 221 #define UxEIE 1 222 #define UxRIE 2 223 #define UxTIE 4 224 225 #define UARTIFS IFS1 226 227 #define UxEIF 1 228 #define UxRIF 2 229 #define UxTIF 4 230 231 #define UARTINTBASE 7 232 #define UARTINTSTEP 14 233 234 #define UART1IPC IPC8 235 #define UART1IPCBASE 0 236 #define UART2IPC IPC9 237 #define UART2IPCBASE 8 238 239 /* Interrupt numbers. 240 * See... 241 * TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION 242 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet 243 */ 244 245 #define DMA0 60 246 #define DMA1 61 247 #define DMA2 62 248 #define DMA3 63 249 #define OC1 7 250 #define OC2 12 251 #define OC3 17 252 #define OC4 22 253 #define OC5 27 254 #define T1 4 255 #define T2 9 256 #define T3 14 257 #define T4 19 258 #define T5 24 259 #define U1RX 40 260 #define U1TX 41 261 #define U2RX 54 262 #define U2TX 55 263 264 /* Address modifiers. 265 * See... 266 * 11.2 CLR, SET and INV Registers 267 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet 268 */ 269 270 #define CLR 0x4 271 #define SET 0x8 272 #define INV 0xC 273 274 #endif /* __PIC32_H__ */