CommonPIC32

docs/wiki/Examples--vga-timer

150:82a63936a118
2019-06-11 Paul Boddie Added initial library documentation.
     1 = VGA Output Example (Timed DMA Transfers) =     2      3 This example demonstrates the generation of an analogue [[VGA Signal Output|     4 VGA]] signal from a PIC32 microcontroller using general output pins. Unlike     5 the [[../vga|vga]] and [[../vga-pmp|vga-pmp]] examples, it employs a regular     6 interrupt condition to schedule single-byte (single-pixel) DMA transfers     7 instead of a single whole-line transfer.     8      9 The principal advantage of this method over the whole-line transfer method is    10 its production of pixels with consistent widths. The principal disadvantage is    11 the significant loss of horizontal resolution due to the latencies involved in    12 propagating interrupt conditions to the DMA controller and thereby initiating    13 each transfer.    14     15 Employing a peripheral clock that has half the frequency of the system clock    16 should ensure the stability of the picture, since the lower frequency may make    17 transfers easier to schedule. The peripheral clock should provide a more    18 forgiving deadline for each transfer, permitting late transfers to complete on    19 time.    20     21 Meanwhile, matching the system and peripheral clock frequencies appears to    22 leave the scheduling of transfers open to uncertainty, with transfers being    23 more readily delayed by other activity in the system, and with instability of    24 the picture being the result.    25     26 Unlike the [[../vga|vga]] example, but in common with the    27 [[../vga-dual|vga-dual]] example, this example employs two DMA channels for    28 pixel data which are interleaved to investigate a potential remedy for the    29 wide pixel effect. This seems to preserve consistent pixel widths only with a    30 transfer cell size of 1: other cell sizes suffer from the wide pixel problem.    31 Despite not offering the greater throughput of larger cell sizes, merely    32 employing dual channels increases throughput for a cell size of 1, making the    33 technique worth using.    34     35 In contrast to the [[../vga|vga]] and [[../vga-pmp|vga-pmp]] examples, a    36 special DMA channel is employed to initiate the pixel transfer process without    37 actually transferring any pixel data itself. The channel arrangement is as    38 follows:    39     40 || Transfer Initiator || DMA Channel || Transfer Activity ||    41 || Timer2             || DMA1        || zerodata -> PORTB ||    42 || Timer3             || DMA0        || linedata -> PORTB ||    43 || Timer3             || DMA2        || linedata -> PORTB ||    44 || Timer3             || DMA3        || zerodata -> PORTB ||    45     46 The real purpose of this channel (DMA1) is to capture the Timer2 interrupt    47 condition and to enable the following channels (DMA0, DMA2) through channel    48 chaining.  Having been enabled, DMA0 and DMA2 are then able to conduct    49 transfers at a tempo dictated by Timer3. Finally, DMA3 acts as the "reset" or    50 "zero" channel to ensure that the pixel level is set to black at the end of    51 each display line.    52     53 In principle, other initiating conditions can be used instead of Timer3, which    54 is configured to produce such conditions as frequently as possible:     55     56   * A persistent interrupt condition can be employed instead. For example,    57     configuring UART2 and setting the UART2 transfer interrupt, employing this    58     interrupt condition for DMA0 and DMA2, produces the same effect.    59     60   * An external interrupt such as INT2 can be configured, and the peripheral    61     clock can be routed through the CLKO pin and back into the microcontroller    62     via an appropriate pin. With INT2 being employed as the interrupt    63     condition for DMA0 and DMA2, the same effect is produced.    64     65 == Hardware Details ==    66     67 The pin usage of this solution is documented below.    68     69 === PIC32MX270F256B-50I/SP Pin Assignments ===    70     71 {{{    72 MCLR#          1  \/  28    73 HSYNC/OC1/RA0  2      27    74 VSYNC/OC2/RA1  3      26 RB15/U1TX    75        D0/RB0  4      25 RB14    76        D1/RB1  5      24 RB13/U1RX    77        D2/RB2  6      23    78        D3/RB3  7      22 RB11/PGEC2    79                8      21 RB10/PGEC3    80           RA2  9      20    81           RA3 10      19    82        D4/RB4 11      18 RB9    83               12      17 RB8    84               13      16 RB7/D7    85        D5/RB5 14      15    86 }}}    87     88 Note that RB6 is not available on pin 15 on this device (it is needed for VBUS    89 unlike the MX170 variant).    90     91 === UART Connections ===    92     93 UART1 is exposed by the RB13 and RB15 pins.    94     95 === Data Signal Routing ===    96     97 For one bit of intensity, two bits per colour channel:    98     99 {{{   100 D7 -> 2200R -> I   101    102 I -> diode -> R   103 I -> diode -> G   104 I -> diode -> B   105    106 D6 (not connected)   107    108 D5 -> 470R -> R   109 D4 -> 1000R -> R   110 D3 -> 470R -> G   111 D2 -> 1000R -> G   112 D1 -> 470R -> B   113 D0 -> 1000R -> B   114    115 HSYNC -> HS   116 VSYNC -> VS   117 }}}