CommonPIC32

docs/wiki/Library--cpu

154:c8a37eb47211
2021-12-14 Paul Boddie Fixed pin labels: RB10/PGEC3 should be RB10/PGED2.
     1 = Low-Level CPU Routines =     2      3 The `lib/cpu.S` file contains low-level routines for handling specific     4 conditions related to the operation of the CPU:     5      6  `init_interrupts`   :: Configures the location of exception and interrupt     7                         vectors.     8      9  `enable_interrupts` :: Enables the delivery of interrupts to the configured    10                         non-bootloader vectors.    11     12  `handle_error_level`:: Handles the initial state of the CPU, making exception    13                         and interrupt conditions possible.    14     15 These routines are called in an appropriate order in the general [[../init|    16 initialisation]] code.    17     18 To support exceptions and interrupts, the following routines are defined in    19 the `.vectors` section of the payload:    20     21  `ebase`       :: Handles TLB exceptions, jumping to the general exception    22                   handler. The PIC32 products tested with this software do not    23                   provide hardware that should raise such exceptions, however.    24     25  `exc_handler` :: Handles exception conditions, switching to a dedicated stack    26                   and jumping to the `exception_handler` routine defined by an    27                   application.    28     29  `int_handler` :: Handles interrupt conditions, switching to a dedicated    30                   stack, saving register values, jumping to the    31                   `interrupt_handler` routine defined by an application, then    32                   restoring register values, switching back to the application    33                   stack and returning to the interrupted code.