1 /* 2 * Device configuration. 3 * 4 * Copyright (C) 2018 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 3 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __CONFIG_H__ 21 #define __CONFIG_H__ 22 23 #include "pic32.h" 24 25 /* 26 Set the oscillator to be the FRC oscillator with PLL, with peripheral clock 27 divided by 2 (FPBDIV), and FRCDIV+PLL selected (FNOSC). 28 29 The watchdog timer (FWDTEN) is also disabled. 30 31 The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with 32 RPB4. 33 */ 34 35 #define DEVCFG1_CONFIG (DEVCFG1_FWDTEN_OFF | DEVCFG1_FPBDIV_2 | \ 36 DEVCFG1_OSCIOFNC_OFF | DEVCFG1_FSOSCEN_OFF | \ 37 DEVCFG1_FNOSC_FRCDIV_PLL) 38 39 /* 40 Set the FRC oscillator PLL function with an input division of 2, an output 41 division of 2, a multiplication of 24, yielding a multiplication of 6. 42 43 The FRC is apparently at 8MHz but enforces input division of 2 to produce a 44 frequency in the acceptable range from 4MHz to 5MHz for the PLL: 45 46 8MHz / 2 = 4MHz 47 48 Multiplication and output division should produce a system clock of 48MHz: 49 50 4MHz * 24 / 2 = 48MHz 51 */ 52 53 #define DEVCFG2_CONFIG (DEVCFG2_FPLLODIV_2 | DEVCFG2_FPLLMUL_24 | \ 54 DEVCFG2_FPLLIDIV_2) 55 56 /* 57 The peripheral clock frequency (FPB) will be 24MHz given the above DEVCFG1 and 58 DEVCFG2 settings. 59 */ 60 61 #define FPB 24000000 62 63 #endif /* __CONFIG_H__ */
