1 = VGA Output Example (Dual-Channel DMA Transfers) = 2 3 This example demonstrates the generation of an analogue VGA signal from a 4 PIC32 microcontroller using general output pins. It follows on from the work 5 done in the VGAPIC32 project. The result is not entirely satisfactory: 6 7 * Every fourth pixel is wider than the others, this apparently being an 8 artefact of the DMA transfer mechanism. 9 10 It might be possible to introduce some kind of delay and even out the pixel 11 widths, but this has not been investigated with hardware. However, unlike the 12 [[../vga-pmp|vga-pmp]] example, there is no accompanying signal to potentially 13 orchestrate the staging of individual pixels at a slightly delayed rate. 14 Potentially, the peripheral clock signal might be generated and processed to 15 make such a signal. 16 17 Unlike the [[../vga|vga]] example, this example employs two DMA channels for 18 pixel data which are interleaved to investigate a potential remedy for the 19 wide pixel effect. Unfortunately, despite each channel contributing every 20 other word (or group of four pixels), the effect persists. However, the 21 picture is perhaps more stable than in the [[../vga|vga]] example. 22 23 One significant problem with this example is that scrolling causes the DMA 24 channels to become ordered incorrectly. This does not affect the 25 [[../vga-timer|vga-timer]] example which also employs two DMA channels. 26 27 == Hardware Details == 28 29 The pin usage of this solution is documented below. 30 31 === PIC32MX270F256B-50I/SP Pin Assignments === 32 33 {{{ 34 MCLR# 1 \/ 28 35 HSYNC/OC1/RA0 2 27 36 VSYNC/OC2/RA1 3 26 RB15/U1TX 37 D0/RB0 4 25 RB14 38 D1/RB1 5 24 RB13/U1RX 39 D2/RB2 6 23 40 D3/RB3 7 22 RB11/PGEC2 41 8 21 RB10/PGEC3 42 RA2 9 20 43 RA3 10 19 44 D4/RB4 11 18 RB9 45 12 17 RB8 46 13 16 RB7/D7 47 D5/RB5 14 15 48 }}} 49 50 Note that RB6 is not available on pin 15 on this device (it is needed for VBUS 51 unlike the MX170 variant). 52 53 === UART Connections === 54 55 UART1 is exposed by the RB13 and RB15 pins. 56 57 === Data Signal Routing === 58 59 For one bit of intensity, two bits per colour channel: 60 61 {{{ 62 D7 -> 2200R -> I 63 64 I -> diode -> R 65 I -> diode -> G 66 I -> diode -> B 67 68 D6 (not connected) 69 70 D5 -> 470R -> R 71 D4 -> 1000R -> R 72 D3 -> 470R -> G 73 D2 -> 1000R -> G 74 D1 -> 470R -> B 75 D0 -> 1000R -> B 76 77 HSYNC -> HS 78 VSYNC -> VS 79 }}} 80 81 === Output Socket Pinout === 82 83 {{{ 84 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R) 85 86 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND) 87 88 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC) 89 }}} 90 91 === Output Cable Pinout === 92 93 {{{ 94 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND) 95 96 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND) 97 98 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC) 99 }}} 100 101 == References == 102 103 https://en.wikipedia.org/wiki/VGA_connector 104 105 http://papilio.cc/index.php?n=Papilio.VGAWing 106 107 http://lucidscience.com/pro-vga%20video%20generator-2.aspx 108 109 https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga