1 /* 2 * PIC32 microcontroller initialisation code. 3 * 4 * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 3 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "mips.h" 21 #include "pic32.h" 22 23 /* Disable JTAG functionality on pins. */ 24 25 .section .devcfg0, "a" 26 .word 0xfffffffb /* DEVCFG0<2> = JTAGEN = 0 */ 27 28 /* 29 Set the oscillator to be the FRC oscillator with PLL, with peripheral clock 30 divided by 2 (FPBDIV), and FRCDIV+PLL selected (FNOSC). 31 32 The watchdog timer (FWDTEN) is also disabled. 33 34 The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with 35 RPB4. 36 */ 37 38 .section .devcfg1, "a" 39 .word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 01; 40 DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */ 41 42 /* 43 Set the FRC oscillator PLL function with an input division of 2, an output 44 division of 2, a multiplication of 24, yielding a multiplication of 6. 45 46 The FRC is apparently at 8MHz but enforces input division of 2 to produce a 47 frequency in the acceptable range from 4MHz to 5MHz for the PLL: 48 49 8MHz / 2 = 4MHz 50 51 Multiplication and output division should produce a system clock of 48MHz: 52 53 4MHz * 24 / 2 = 48MHz 54 55 The peripheral clock frequency (FPB) will be 24MHz given the above DEVCFG1 56 settings. 57 */ 58 59 .section .devcfg2, "a" 60 .word 0xfff9fff9 /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001; 61 DEVCFG2<6:4> = FPLLMUL<2:0> = 111; 62 DEVCFG2<2:0> = FPLLIDIV<2:0> = 001 */ 63 64 /* The start routine is placed at the boot location. */ 65 66 .section .boot, "a" 67 68 .globl _start 69 .extern main 70 71 _start: 72 /* Enable caching. */ 73 74 mfc0 $v1, CP0_CONFIG 75 li $t8, ~CONFIG_K0 76 and $v1, $v1, $t8 77 ori $v1, $v1, CONFIG_K0_CACHABLE_NONCOHERENT 78 mtc0 $v1, CP0_CONFIG 79 nop 80 81 /* Get the RAM size. */ 82 83 la $v1, BMXDRMSZ 84 lw $t0, 0($v1) 85 86 /* Initialise the stack pointer. */ 87 88 li $v1, KSEG0_BASE 89 addu $sp, $t0, $v1 /* sp = KSEG0_BASE + RAM size */ 90 91 /* Initialise the globals pointer. */ 92 93 lui $gp, %hi(_GLOBAL_OFFSET_TABLE_) 94 ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_) 95 96 /* 97 Jump to the main program. Since the boot code is separate from the 98 other code, the address cannot be obtained via the GOT. 99 ("relocation truncated to fit: R_MIPS_PC16 against `main'") 100 */ 101 102 lui $t9, %hi(main) 103 ori $t9, $t9, %lo(main) 104 jr $t9 105 nop