# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1539725177 -7200
# Node ID 1a5dd3cb29ab8ac2d377e1a913d687dcc66aa325

Some tidied-up configuration and initialisation routines and a simple UART test.

diff -r 000000000000 -r 1a5dd3cb29ab Makefile
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Makefile	Tue Oct 16 23:26:17 2018 +0200
@@ -0,0 +1,75 @@
+# Makefile - Build the IntCondTest payload
+#
+# Copyright (C) 2015, 2017, 2018 Paul Boddie <paul@boddie.org.uk>
+# Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+ARCH = mipsel-linux-gnu
+CC = $(ARCH)-gcc
+LD = $(ARCH)-ld
+NM = $(ARCH)-nm
+OBJCOPY=$(ARCH)-objcopy
+OBJDUMP=$(ARCH)-objdump
+
+# NOTE: -O2 is actually needed to prevent memcpy references, whereas probably
+# NOTE: one of the -f{freestanding, no-hosted, no-builtin} options should work.
+# NOTE: See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56888
+
+CFLAGS = -O2 -Wall \
+	-fno-unit-at-a-time -fno-zero-initialized-in-bss \
+	-ffreestanding -fno-hosted -fno-builtin \
+	-march=mips32
+LDFLAGS = -nostdlib -EL
+
+TARGET = intcond.elf
+DUMP = $(TARGET:.elf=.dump)
+MAP = $(TARGET:.elf=.map)
+SCRIPT = $(TARGET:.elf=.ld)
+
+HEX = $(TARGET:.elf=.hex)
+SREC = $(TARGET:.elf=.srec)
+
+# Ordering of objects is important and cannot be left to replacement rules.
+
+SRC = intcond.S main.c init.c cpu.S
+OBJ = intcond.o main.o init.o cpu.o
+
+.PHONY:	all clean distclean
+
+all:	$(HEX) $(SREC)
+
+clean:
+	rm -f $(OBJ) $(TARGET) $(HEX) $(SREC) $(DUMP) *.map
+
+distclean: clean
+	echo "Nothing else to clean."
+
+$(HEX): $(TARGET)
+	$(OBJCOPY) -O ihex $(TARGET) $(HEX)
+
+$(SREC): $(TARGET)
+	$(OBJCOPY) -O srec $(TARGET) $(SREC)
+
+$(TARGET): $(OBJ)
+	$(LD) $(LDFLAGS) -T $(SCRIPT) $(OBJ) -o $@
+	$(OBJDUMP) -D $(TARGET) > $(DUMP)
+	$(OBJDUMP) -h $(TARGET) > $(MAP)
+	$(NM) -n $(TARGET) > System.map
+
+.c.o:
+	$(CC) -c $(CFLAGS) $< -o $@
+
+.S.o:
+	$(CC) -c $(CFLAGS) $< -o $@
diff -r 000000000000 -r 1a5dd3cb29ab cpu.S
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cpu.S	Tue Oct 16 23:26:17 2018 +0200
@@ -0,0 +1,172 @@
+/*
+ * PIC32 microcontroller interrupt handling code.
+ *
+ * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "mips.h"
+#include "pic32.h"
+#include "cpu.h"
+
+.globl enable_interrupts
+.globl handle_error_level
+.globl init_interrupts
+.extern exception_handler
+.extern interrupt_handler
+
+/* Put general routines in the text section. */
+
+.text
+
+/*
+Clear the error and exception status flags, making interrupts and exceptions
+possible.
+*/
+
+handle_error_level:
+        mfc0 $t3, CP0_STATUS
+
+	/* Clear error level and exception level. */
+
+        li $t4, ~(STATUS_ERL | STATUS_EXL)
+        and $t3, $t3, $t4
+        mtc0 $t3, CP0_STATUS
+
+        jr $ra
+        nop
+
+/* Enable interrupts and direct interrupt requests to non-bootloader vectors. */
+
+enable_interrupts:
+        mfc0 $t3, CP0_STATUS
+
+	/* Clear interrupt priority bits. */
+
+        li $t4, ~STATUS_IRQ
+        and $t3, $t3, $t4
+
+	/* Set interrupt priority. */
+
+	ori $t3, $t3, (CPU_INT_PRIORITY << STATUS_IRQ_SHIFT)
+
+	/* CP0_STATUS &= ~STATUS_BEV (use non-bootloader vectors) */
+
+        li $t4, ~STATUS_BEV
+        and $t3, $t3, $t4
+
+	/* Enable interrupts. */
+
+        ori $t3, $t3, STATUS_IE
+        mtc0 $t3, CP0_STATUS
+
+        jr $ra
+        nop
+
+/* Initialise the interrupt system parameters. */
+
+init_interrupts:
+	/* Clear debug mode. */
+
+        mfc0 $t3, CP0_DEBUG
+        li $t4, ~DEBUG_DM
+        and $t3, $t3, $t4
+        mtc0 $t3, CP0_DEBUG
+
+	/* Update the exception base. */
+
+        mfc0 $t3, CP0_STATUS
+        li $t4, STATUS_BEV      /* BEV = 1 or EBASE cannot be set */
+        or $t3, $t3, $t4
+        mtc0 $t3, CP0_STATUS
+
+        la $t3, ebase
+        mtc0 $t3, CP0_EBASE
+
+	/* Set vector spacing. */
+
+        li $t3, 0x20            /* Must be non-zero or the CPU gets upset */
+        mtc0 $t3, CP0_INTCTL
+
+        li $t3, CAUSE_IV        /* IV = 1 (use EBASE+0x200 for interrupts) */
+        mtc0 $t3, CP0_CAUSE
+
+        jr $ra
+        nop
+
+
+
+/* Exception servicing, positioned at EBASE at the start of program memory. */
+
+.section .vectors, "a"
+
+/* TLB error servicing. */
+
+ebase:
+tlb_handler:
+        j exception_handler
+        nop
+
+
+
+/* General exception servicing. */
+
+.org 0x180
+
+exc_handler:
+        j exception_handler
+        nop
+
+
+
+/* Interrupt servicing. */
+
+.org 0x200
+.set noat
+
+#define IRQ_STACK_LIMIT	(KSEG0_BASE + 256)
+#define IRQ_STACK_TOP	(IRQ_STACK_LIMIT - 32 * 4)
+
+int_handler:
+
+        /* Store affected registers from IRQ_STACK_LIMIT - 4 downwards. */
+
+        li $k0, IRQ_STACK_LIMIT
+
+	.irp reg, \
+		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 \
+		16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
+		28, 29, 30, 31
+		sw $\reg, -(\reg * 4)($k0)
+	.endr
+
+	/* Switch to the IRQ stack. */
+
+        li $sp, IRQ_STACK_TOP
+
+	jal interrupt_handler
+	nop
+
+        /* Restore affected registers. */
+
+	.irp reg, \
+		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 \
+		16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
+		28, 29, 30, 31
+		lw $\reg, -(\reg * 4)($k0)
+	.endr
+
+        eret
+        nop
diff -r 000000000000 -r 1a5dd3cb29ab cpu.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/cpu.h	Tue Oct 16 23:26:17 2018 +0200
@@ -0,0 +1,16 @@
+#ifndef __CPU_H__
+#define __CPU_H__
+
+#define CPU_INT_PRIORITY 3
+
+#ifndef __ASSEMBLER__
+
+/* Specific operations. */
+
+void enable_interrupts(void);
+void handle_error_level(void);
+void init_interrupts(void);
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __CPU_H__ */
diff -r 000000000000 -r 1a5dd3cb29ab init.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/init.c	Tue Oct 16 23:26:17 2018 +0200
@@ -0,0 +1,126 @@
+#include "cpu.h"
+#include "pic32_c.h"
+
+
+
+/* Basic memory and pin initialisation. */
+
+void init_memory(void)
+{
+    /*
+    Configure RAM.
+    See: http://microchipdeveloper.com/32bit:mx-arch-exceptions-processor-initialization
+    */
+
+    uint32_t config = REG(BMXCON);
+
+    /* Set zero wait states for address setup. */
+
+    config &= ~(1 << 6);        /* BMXCON<6> = BMXWSDRM = 0 */
+
+    /* Set bus arbitration mode. */
+
+    config &= ~0b111;
+    config |= 0b010;            /* BMXCON<2:0> = BMXARB<2:0> = 2 */
+
+    REG(BMXCON) = config;
+}
+
+void init_pins(void)
+{
+    /* DEVCFG0<2> also needs setting to 0 before the program is run. */
+
+    CLR_REG(CFGCON, 1 << 3);    /* CFGCON<3> = JTAGEN = 0 */
+}
+
+void init_outputs(void)
+{
+    /* Remove analogue features from pins. */
+
+    REG(ANSELA) = 0;
+    REG(ANSELB) = 0;
+
+    REG(TRISA) = 0;
+    REG(TRISB) = 0;
+
+    REG(PORTA) = 0;
+    REG(PORTB) = 0;
+}
+
+
+
+/* Peripheral pin configuration. */
+
+void config_uart(void)
+{
+    /* Map U1RX to RPB13. */
+
+    REG(U1RXR) = 0b0011;        /* U1RXR<3:0> = 0011 (RPB13) */
+
+    /* Map U1TX to RPB15. */
+
+    REG(RPB15R) = 0b0001;       /* RPB15R<3:0> = 0001 (U1TX) */
+
+    /* Set RPB13 to input. */
+
+    SET_REG(TRISB, 1 << 13);
+}
+
+void lock_config(void)
+{
+    SET_REG(CFGCON, 1 << 13);   /* IOLOCK = 1 */
+
+    /* Lock the configuration again. */
+
+    REG(SYSKEY) = 0x33333333;
+}
+
+void unlock_config(void)
+{
+    /* Unlock the configuration register bits. */
+
+    REG(SYSKEY) = 0;
+    REG(SYSKEY) = 0xAA996655;
+    REG(SYSKEY) = 0x556699AA;
+
+    CLR_REG(CFGCON, 1 << 13);   /* IOLOCK = 0 */
+}
+
+
+
+/* Convenience operations. */
+
+void interrupts_on(void)
+{
+    init_interrupts();
+    enable_interrupts();
+    handle_error_level();
+}
+
+
+
+/* Peripheral configuration. */
+
+void init_uart(uint8_t pri, uint8_t sub)
+{
+    CLR_REG(U1MODE, 1 << 15);   /* U1MODE<15> = ON = 0 */
+    REG(U1BRG) = 12;            /* U1BRG<15:0> = BRG = (FPB / (16 * baudrate)) - 1 = (24000000 / (16 * 115200)) - 1 = 12 */
+
+    /* Disable interrupt and clear flag. */
+
+    CLR_REG(IEC1, 1 << 8);      /* IEC1<8> = U1RIE = 0 */
+    CLR_REG(IFS1, 1 << 8);      /* IFS1<8> = U1RIF = 0 */
+
+    /* Set priorities: U1IP = pri; U1IS = sub */
+
+    REG(IPC8) = (REG(IPC8) & ~0b11111) | ((pri & 0b111) << 2) | (sub & 0b11);
+
+    /* Enable interrupt. */
+
+    SET_REG(IEC1, 1 << 8);      /* IEC1<8> = U1RIE = 1 */
+
+    /* Start UART. */
+
+    SET_REG(U1STA, (1 << 12) | (1 << 10));  /* U1STA<12> = URXEN = 1; U1STA<10> = UTXEN = 1 */
+    SET_REG(U1MODE, 1 << 15);               /* U1MODE<15> = ON = 1 */
+}
diff -r 000000000000 -r 1a5dd3cb29ab init.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/init.h	Tue Oct 16 23:26:17 2018 +0200
@@ -0,0 +1,24 @@
+#ifndef __INIT_H__
+#define __INIT_H__
+
+/* Basic initialisation. */
+
+void init_memory(void);
+void init_pins(void);
+void init_outputs(void);
+
+/* Peripheral pin configuration. */
+
+void config_uart(void);
+void lock_config(void);
+void unlock_config(void);
+
+/* Convenience operations. */
+
+void interrupts_on(void);
+
+/* Peripheral configuration. */
+
+void init_uart(uint8_t pri, uint8_t sub);
+
+#endif /* __INIT_H__ */
diff -r 000000000000 -r 1a5dd3cb29ab intcond.S
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/intcond.S	Tue Oct 16 23:26:17 2018 +0200
@@ -0,0 +1,95 @@
+/*
+ * PIC32 microcontroller initialisation code.
+ *
+ * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "mips.h"
+#include "pic32.h"
+
+/* Disable JTAG functionality on pins. */
+
+.section .devcfg0, "a"
+.word 0xfffffffb	/* DEVCFG0<2> = JTAGEN = 0 */
+
+/*
+Set the oscillator to be the FRC oscillator with PLL, with peripheral clock
+divided by 2, and FRCDIV+PLL selected.
+
+The watchdog timer (FWDTEN) is also disabled.
+
+The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with
+RPB4.
+*/
+
+.section .devcfg1, "a"
+.word 0xff7fdfd9	/* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
+			DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
+
+/*
+Set the FRC oscillator PLL function with an input division of 4, an output
+division of 2, a multiplication of 24, yielding a multiplication of 3.
+
+The FRC is apparently at 16MHz and this produces a system clock of 48MHz.
+*/
+
+.section .devcfg2, "a"
+.word 0xfff9fffb	/* DEVCFG2<18:16> = FPLLODIV<2:0> = 001;
+			DEVCFG2<6:4> = FPLLMUL<2:0> = 111;
+			DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */
+
+/* The start routine is placed at the boot location. */
+
+.section .boot, "a"
+
+.globl _start
+.extern main
+
+_start:
+	/* Enable caching. */
+
+	mfc0 $v1, CP0_CONFIG
+	li $t8, ~CONFIG_K0
+	and $v1, $v1, $t8
+	ori $v1, $v1, CONFIG_K0_CACHABLE_NONCOHERENT
+	mtc0 $v1, CP0_CONFIG
+	nop
+
+	/* Get the RAM size. */
+
+	la $v1, BMXDRMSZ
+	lw $t0, 0($v1)
+
+        /* Initialise the stack pointer. */
+
+        li $v1, KSEG0_BASE
+        addu $sp, $t0, $v1      /* sp = KSEG0_BASE + RAM size */
+
+        /* Initialise the globals pointer. */
+
+        lui $gp, %hi(_GLOBAL_OFFSET_TABLE_)
+        ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_)
+
+	/*
+	Jump to the main program. Since the boot code is separate from the
+	other code, the address cannot be obtained via the GOT.
+	("relocation truncated to fit: R_MIPS_PC16 against `main'")
+	*/
+
+        lui $t9, %hi(main)
+        ori $t9, $t9, %lo(main)
+	jr $t9
+	nop
diff -r 000000000000 -r 1a5dd3cb29ab intcond.ld
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/intcond.ld	Tue Oct 16 23:26:17 2018 +0200
@@ -0,0 +1,42 @@
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+
+/* See...
+ * FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX170/270 DEVICES (64 KB RAM, 256 KB FLASH)
+ * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet
+ */
+
+MEMORY
+{
+  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x10000
+  kseg0_boot_mem       (rx)  : ORIGIN = 0x9FC00000, LENGTH = 0xBF0
+  kseg0_program_mem    (rx)  : ORIGIN = 0x9D000000, LENGTH = 0x40000
+  physical_boot_mem    (rx)  : ORIGIN = 0x1FC00000, LENGTH = 0xBF0
+  physical_program_mem (rx)  : ORIGIN = 0x1D000000, LENGTH = 0x40000
+  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000
+  configsfrs                 : ORIGIN = 0xBFC00BF0, LENGTH = 0x10
+  config3                    : ORIGIN = 0xBFC00BF0, LENGTH = 0x4
+  config2                    : ORIGIN = 0xBFC00BF4, LENGTH = 0x4
+  config1                    : ORIGIN = 0xBFC00BF8, LENGTH = 0x4
+  config0                    : ORIGIN = 0xBFC00BFC, LENGTH = 0x4
+  physical_config3           : ORIGIN = 0x3FC00BF0, LENGTH = 0x4
+  physical_config2           : ORIGIN = 0x3FC00BF4, LENGTH = 0x4
+  physical_config1           : ORIGIN = 0x3FC00BF8, LENGTH = 0x4
+  physical_config0           : ORIGIN = 0x3FC00BFC, LENGTH = 0x4
+}
+
+SECTIONS
+{
+  .boot     : { *(.boot*) }     > kseg0_boot_mem    AT > physical_boot_mem
+  .vectors  : { *(.vectors*) }  > kseg0_program_mem AT > physical_program_mem
+  .text     : { *(.text*) }     > kseg0_program_mem AT > physical_program_mem
+  .bss      : { *(.bss*)  }     > kseg1_data_mem
+  .got      : {
+                _gp = ALIGN(16);
+                *(.got*)
+              }                 > kseg0_program_mem AT > physical_program_mem
+  .devcfg0  : { *(.devcfg0) }   > config0           AT > physical_config0
+  .devcfg1  : { *(.devcfg1) }   > config1           AT > physical_config1
+  .devcfg2  : { *(.devcfg2) }   > config2           AT > physical_config2
+  /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) }
+}
diff -r 000000000000 -r 1a5dd3cb29ab main.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/main.c	Tue Oct 16 23:26:17 2018 +0200
@@ -0,0 +1,85 @@
+#include "pic32_c.h"
+#include "init.h"
+
+static void uart_write(char c)
+{
+    while (REG(U1STA) & (1 << 9));  /* UTXBF (buffer full) */
+
+    REG(U1TXREG) = c;
+}
+
+static void bits(uint32_t reg)
+{
+    uint32_t mask;
+
+    for (mask = (1 << 31); mask; mask >>= 1)
+        if (REG(reg) & mask)
+            uart_write('1');
+        else
+            uart_write('0');
+
+    uart_write('\r');
+    uart_write('\n');
+}
+
+static void blink(uint32_t delay, uint32_t port, uint32_t pins)
+{
+    uint32_t counter;
+
+    /* Clear outputs (LED). */
+
+    CLR_REG(port, pins);
+
+    while (1)
+    {
+        counter = delay;
+
+        while (counter--) __asm__("");	/* retain loop */
+
+        /* Invert outputs (LED). */
+
+        INV_REG(port, pins);
+        bits(IFS1);
+    }
+}
+
+void main(void)
+{
+    init_memory();
+    init_pins();
+    init_outputs();
+
+    unlock_config();
+    config_uart();
+    lock_config();
+
+    init_uart(7, 3);
+
+    interrupts_on();
+
+    blink(3 << 24, PORTA, 1 << 3);
+}
+
+void exception_handler(void)
+{
+    blink(3 << 12, PORTA, 1 << 3);
+}
+
+void interrupt_handler(void)
+{
+    /* Check for a UART receive interrupt condition (U1RIF). */
+
+    if (!(REG(IFS1) & (1 << 8)))
+        return;
+
+    /* Write the received data back. */
+
+    INV_REG(PORTA, 1 << 2);
+
+    while (REG(U1STA) & 1)
+        uart_write((char) REG(U1RXREG));
+
+    /* Clear the UART interrupt condition. */
+
+    CLR_REG(IFS1, 1 << 8);
+}
diff -r 000000000000 -r 1a5dd3cb29ab mips.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mips.h	Tue Oct 16 23:26:17 2018 +0200
@@ -0,0 +1,63 @@
+#ifndef __MIPS_H__
+#define __MIPS_H__
+
+#define KSEG0_BASE	0x80000000
+#define KSEG1_BASE	0xA0000000
+
+#define CP0_INDEX	$0
+#define CP0_ENTRYLO0	$2
+#define CP0_ENTRYLO1	$3
+#define CP0_CONTEXT	$4
+#define CP0_PAGEMASK	$5
+#define CP0_WIRED	$6
+#define CP0_BADVADDR	$8
+#define CP0_COUNT	$9
+#define CP0_ENTRYHI	$10
+#define CP0_COMPARE	$11
+#define CP0_STATUS	$12
+#define CP0_INTCTL	$12, 1
+#define CP0_CAUSE	$13
+#define CP0_EPC		$14
+#define CP0_EBASE	$15, 1
+#define CP0_CONFIG	$16
+#define CP0_WATCHLO	$18
+#define CP0_DEBUG	$23
+#define CP0_TAGLO	$28
+#define CP0_TAGHI	$29
+#define CP0_ERROREPC	$30, 0
+
+#define STATUS_CP0	0x10000000
+#define STATUS_BEV	0x00400000
+
+#define STATUS_IRQ	0x0000fc00
+#define STATUS_IRQ_SHIFT	10
+
+#define STATUS_UM	0x00000010
+#define STATUS_ERL	0x00000004
+#define STATUS_EXL	0x00000002
+#define STATUS_IE	0x00000001
+
+#define CAUSE_IV	0x00800000
+
+#define EBASE_MASK	0x3ffff000
+
+#define INTCTL_MASK	0x000003e0
+
+#define DEBUG_DM	0x40000000
+
+#define TLB_CACHED	0x00000018
+#define TLB_UNCACHED	0x00000010
+#define TLB_DIRTY	0x00000004
+#define TLB_VALID	0x00000002
+#define TLB_GLOBAL	0x00000001
+
+#define TLB_READ	(TLB_CACHED | TLB_VALID)
+#define TLB_WRITE	(TLB_CACHED | TLB_DIRTY | TLB_VALID)
+#define TLB_ALL_READ	(TLB_CACHED | TLB_VALID | TLB_GLOBAL)
+#define TLB_ALL_WRITE	(TLB_CACHED | TLB_DIRTY | TLB_VALID | TLB_GLOBAL)
+
+#define CONFIG_K0	0x00000007
+#define CONFIG_K0_UNCACHED		2
+#define CONFIG_K0_CACHABLE_NONCOHERENT	3
+
+#endif /* __MIPS_H__ */
diff -r 000000000000 -r 1a5dd3cb29ab pic32.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/pic32.h	Tue Oct 16 23:26:17 2018 +0200
@@ -0,0 +1,125 @@
+#ifndef __PIC32_H__
+#define __PIC32_H__
+
+/* See...
+ * TABLE 4-1: SFR MEMORYMAP
+ * TABLE 11-3: PORTA REGISTER MAP
+ * 11.2 CLR, SET and INV Registers
+ * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet
+ */
+
+#define OC1CON		0xBF803000
+#define OC1R		0xBF803010
+#define OC1RS		0xBF803020
+#define OC2CON		0xBF803200
+#define OC2R		0xBF803210
+#define OC2RS		0xBF803220
+#define OC3CON		0xBF803400
+#define OC3R		0xBF803410
+#define OC3RS		0xBF803420
+
+#define T1CON   	0xBF800600
+#define TMR1    	0xBF800610
+#define PR1     	0xBF800620
+#define T2CON   	0xBF800800
+#define TMR2    	0xBF800810
+#define PR2     	0xBF800820
+#define T3CON   	0xBF800A00
+#define TMR3    	0xBF800A10
+#define PR3     	0xBF800A20
+
+#define U1MODE		0xBF806000
+#define U1STA		0xBF806010
+#define U1TXREG		0xBF806020
+#define U1RXREG		0xBF806030
+#define U1BRG		0xBF806040
+
+#define PMCON 		0xBF807000
+#define PMMODE		0xBF807010
+#define PMADDR		0xBF807020
+#define PMDOUT		0xBF807030
+#define PMDIN 		0xBF807040
+#define PMAEN 		0xBF807050
+#define PMSTAT		0xBF807060
+
+#define OSCCON		0xBF80F000
+#define REFOCON		0xBF80F020
+#define REFOTRIM	0xBF80F030
+#define CFGCON		0xBF80F200
+#define SYSKEY		0xBF80F230
+
+#define U1RXR		0xBF80FA50
+
+#define RPA0R		0xBF80FB00
+#define RPA1R		0xBF80FB04
+#define RPA2R		0xBF80FB08
+#define RPA3R		0xBF80FB0C
+#define RPA4R		0xBF80FB10
+#define RPB0R		0xBF80FB2C
+#define RPB1R		0xBF80FB30
+#define RPB2R		0xBF80FB34
+#define RPB3R		0xBF80FB38
+#define RPB4R		0xBF80FB3C
+#define RPB5R		0xBF80FB40
+#define RPB10R		0xBF80FB54
+#define RPB15R		0xBF80FB68
+
+#define INTCON		0xBF881000
+#define IFS0		0xBF881030
+#define IFS1		0xBF881040
+#define IEC0		0xBF881060
+#define IEC1		0xBF881070
+#define IPC1		0xBF8810A0
+#define IPC2		0xBF8810B0
+#define IPC7		0xBF881100
+#define IPC8		0xBF881110
+#define IPC10		0xBF881130
+
+#define BMXCON		0xBF882000
+#define BMXDKPBA	0xBF882010
+#define BMXDUDBA	0xBF882020
+#define BMXDUPBA	0xBF882030
+#define BMXDRMSZ	0xBF882040
+
+#define DMACON		0xBF883000
+#define DCH0CON		0xBF883060
+#define DCH0ECON	0xBF883070
+#define DCH0INT		0xBF883080
+#define DCH0SSA		0xBF883090
+#define DCH0DSA		0xBF8830A0
+#define DCH0SSIZ	0xBF8830B0
+#define DCH0DSIZ	0xBF8830C0
+#define DCH0CSIZ	0xBF8830F0
+#define DCH1CON		0xBF883120
+#define DCH1ECON	0xBF883130
+#define DCH1INT		0xBF883140
+#define DCH1SSA		0xBF883150
+#define DCH1DSA		0xBF883160
+#define DCH1SSIZ	0xBF883170
+#define DCH1DSIZ	0xBF883180
+#define DCH1CSIZ	0xBF8831B0
+#define DCH2CON		0xBF8831E0
+#define DCH2ECON	0xBF8831F0
+#define DCH2INT		0xBF883200
+#define DCH2SSA		0xBF883210
+#define DCH2DSA		0xBF883220
+#define DCH2SSIZ	0xBF883230
+#define DCH2DSIZ	0xBF883240
+#define DCH2CSIZ	0xBF883270
+
+#define ANSELA		0xBF886000
+#define TRISA		0xBF886010
+#define PORTA		0xBF886020
+#define LATA		0xBF886030
+#define ODCA		0xBF886040
+#define ANSELB		0xBF886100
+#define TRISB		0xBF886110
+#define PORTB		0xBF886120
+#define LATB		0xBF886130
+#define ODCB		0xBF886140
+
+#define CLR 0x4
+#define SET 0x8
+#define INV 0xC
+
+#endif /* __PIC32_H__ */
diff -r 000000000000 -r 1a5dd3cb29ab pic32_c.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/pic32_c.h	Tue Oct 16 23:26:17 2018 +0200
@@ -0,0 +1,21 @@
+#ifndef __ASSEMBLER__
+
+#ifndef __PIC32_C_H__
+#define __PIC32_C_H__
+
+#include <stdint.h>
+#include "pic32.h"
+
+/* Access. */
+
+#define REG(mem)		*((volatile uint32_t *) (mem))
+
+/* Bit clearing, setting and inverting. */
+
+#define CLR_REG(mem, val)	(REG(mem + CLR) = val)
+#define SET_REG(mem, val)	(REG(mem + SET) = val)
+#define INV_REG(mem, val)	(REG(mem + INV) = val)
+
+#endif /* __PIC32_C_H__ */
+
+#endif /* __ASSEMBLER__ */