# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1586804141 -7200
# Node ID 5def8be211f41dcc414d4a603fdd7be488eb9ae8
# Parent  82a63936a118754c8862e2d6cac2c9247b04b197
Added a diagram of the output routing from pins to the socket.

diff -r 82a63936a118 -r 5def8be211f4 docs/wiki/VGA_Signal_Wiring
--- a/docs/wiki/VGA_Signal_Wiring	Tue Jun 11 16:49:23 2019 +0200
+++ b/docs/wiki/VGA_Signal_Wiring	Mon Apr 13 20:55:41 2020 +0200
@@ -5,6 +5,100 @@
 these are certain hardware characteristics, described here to avoid
 unnecessary repetition.
 
+== Data Signal Routing ==
+
+The following routing from output pins to output socket pins is employed.
+
+{{{#!graphviz
+//format=svg
+//transform=notugly
+digraph routing {
+  graph [ranksep=1.0,style=invis,fontsize="15.0",fontname="Helvetica",splines=ortho];
+  node [shape=box,style=filled,fillcolor=white,fontsize="13.0",fontname="Helvetica"];
+  rankdir=LR;
+
+  /* Output pins. */
+
+  subgraph {
+    rank=same;
+    pins [label="Output pins",shape=note,fillcolor=gold];
+    D6 [fillcolor=lightgrey];
+    D5 [fillcolor="#ff7777"];
+    D4 [fillcolor="#ff7777"];
+    D3 [fillcolor="#77ff77"];
+    D2 [fillcolor="#77ff77"];
+    D1 [fillcolor="#7777ff"];
+    D0 [fillcolor="#7777ff"];
+    D7 -> D6 -> D5 -> D4 -> D3 -> D2 -> D1 -> D0 -> HSYNC -> VSYNC -> pins [style=invis];
+  }
+
+  /* Intensity adjustment resistor. */
+
+  I2 [label="2200R"];
+
+  /* Colour channel resistors and diodes. */
+
+  subgraph {
+    rank=same;
+    R2 [label="470R",fillcolor="#ff7777"];
+    R1 [label="1000R",fillcolor="#ff7777"];
+    RD [label="diode",fillcolor="#ff7777"];
+    R2 -> R1 -> RD [style=invis];
+  }
+
+  subgraph {
+    rank=same;
+    G2 [label="470R",fillcolor="#77ff77"];
+    G1 [label="1000R",fillcolor="#77ff77"];
+    GD [label="diode",fillcolor="#77ff77"];
+    G2 -> G1 -> GD [style=invis];
+  }
+
+  subgraph {
+    rank=same;
+    B2 [label="470R",fillcolor="#7777ff"];
+    B1 [label="1000R",fillcolor="#7777ff"];
+    BD [label="diode",fillcolor="#7777ff"];
+    B2 -> B1 -> BD [style=invis];
+  }
+
+  /* Video signals. */
+
+  subgraph {
+    rank=same;
+    signals [label="Video signals",shape=note,fillcolor=gold];
+    R [fillcolor="#ff7777"];
+    G [fillcolor="#77ff77"];
+    B [fillcolor="#7777ff"];
+    R -> G -> B -> HS -> VS -> signals [style=invis];
+  }
+
+  D7 -> I2;
+  D6 /* not connected */
+  D5 -> R2 -> R;
+  D4 -> R1 -> R;
+  D3 -> G2 -> G;
+  D2 -> G1 -> G;
+  D1 -> B2 -> B;
+  D0 -> B1 -> B;
+
+  I2 -> RD;
+  I2 -> GD;
+  I2 -> BD;
+
+  RD -> R;
+  GD -> G;
+  BD -> B;
+
+  HSYNC -> HS;
+  VSYNC -> VS;
+}
+}}}
+
+Where two bits of intensity are supported, D6 is routed via a 4700 ohm
+resistor to each of the colour channel diodes, contributing to the existing
+D7-driven intensity signal.
+
 == Pinouts ==
 
 For the examples documented in this project, the following pinouts apply. VGA