1.1 --- a/main.c Thu Oct 18 21:04:00 2018 +0200
1.2 +++ b/main.c Thu Oct 18 21:05:18 2018 +0200
1.3 @@ -2,7 +2,8 @@
1.4 #include "init.h"
1.5 #include "debug.h"
1.6
1.7 -static const char message[] = "Hello!\r\n";
1.8 +static const char message1[] = "Hello!\r\n";
1.9 +static const char message2[] = "Again!\r\n";
1.10 static int uart_echo = 0;
1.11
1.12 static void blink(uint32_t delay, uint32_t port, uint32_t pins)
1.13 @@ -37,22 +38,40 @@
1.14
1.15 init_dma();
1.16
1.17 - /* Initiate DMA on UART receive interrupt, raising transfer completion
1.18 - interrupt. Since the channel is not auto-enabled, it must be explicitly
1.19 - enabled upon completion. */
1.20 + /* Initiate DMA on the Timer2 interrupt. Since the channel is not
1.21 + auto-enabled, it must be explicitly enabled upon completion. */
1.22
1.23 dma_init(0, 3);
1.24 - dma_set_interrupt(0, U1RX, 1);
1.25 - dma_set_transfer(0, PHYSICAL((uint32_t) message), sizeof(message) - 1,
1.26 + dma_set_interrupt(0, T2, 1);
1.27 + dma_set_transfer(0, PHYSICAL((uint32_t) message1), sizeof(message1) - 1,
1.28 + HW_PHYSICAL(UART_REG(1, UxTXREG)), 1,
1.29 + 1);
1.30 +
1.31 + /* Enable DMA on the preceding channel's completion, with Timer3 initiating
1.32 + transfers, raising a transfer completion interrupt. */
1.33 +
1.34 + dma_init(1, 3);
1.35 + dma_set_chaining(1, dma_chain_previous);
1.36 + dma_set_interrupt(1, T3, 1);
1.37 + dma_set_transfer(1, PHYSICAL((uint32_t) message2), sizeof(message2) - 1,
1.38 HW_PHYSICAL(UART_REG(1, UxTXREG)), 1,
1.39 1);
1.40 - dma_init_interrupt(0, 0b00001000, 7, 3);
1.41 - dma_on(0);
1.42 + dma_init_interrupt(1, 0b00001000, 7, 3);
1.43 +
1.44 + /* Configure timers. */
1.45
1.46 - /* Set UART interrupt priority below CPU priority. */
1.47 + timer_init(2, 0b111, 60000);
1.48 + timer_init_interrupt(2, 1, 3);
1.49 + timer_on(2);
1.50 +
1.51 + timer_init(3, 0b111, 40000);
1.52 + timer_init_interrupt(3, 1, 3);
1.53 + timer_on(3);
1.54 +
1.55 + /* Set UART interrupt priority above CPU priority to process events. */
1.56
1.57 uart_init(1, 115200);
1.58 - uart_init_interrupt(1, UxRIF, 1, 3);
1.59 + uart_init_interrupt(1, UxRIF, 7, 3);
1.60 uart_on(1);
1.61
1.62 interrupts_on();
1.63 @@ -86,12 +105,17 @@
1.64 val = REG(UART_REG(1, UxRXREG));
1.65 if (uart_echo)
1.66 uart_write((char) val);
1.67 +
1.68 + /* Initiate transfer upon receiving a particular character. */
1.69 +
1.70 + if (val == '0')
1.71 + dma_on(0);
1.72 }
1.73 }
1.74
1.75 /* Check for a DMA interrupt condition (CHBCIF). */
1.76
1.77 - ifs = REG(DMAIFS) & DMA_INT_FLAGS(0, 1);
1.78 + ifs = REG(DMAIFS) & DMA_INT_FLAGS(1, 1);
1.79
1.80 if (ifs)
1.81 {