1.1 --- a/main.c Fri Oct 19 17:13:56 2018 +0200
1.2 +++ b/main.c Fri Oct 19 17:50:59 2018 +0200
1.3 @@ -85,6 +85,7 @@
1.4 dma_set_transfer(1, PHYSICAL((uint32_t) message2), sizeof(message2) - 1,
1.5 HW_PHYSICAL(UART_REG(1, UxTXREG)), 1,
1.6 1);
1.7 + dma_init_interrupt(1, 0b00001000, 7, 3);
1.8
1.9 /* Configure a timer for the first DMA channel whose interrupt condition
1.10 drives the transfer but is not handled (having a lower priority than the
1.11 @@ -157,6 +158,18 @@
1.12 dma_on(0);
1.13 }
1.14 }
1.15 +
1.16 + /* Check for a DMA interrupt condition (CHBCIF). */
1.17 +
1.18 + ifs = REG(DMAIFS) & DMA_INT_FLAGS(1, 1);
1.19 +
1.20 + if (ifs)
1.21 + {
1.22 + uart_write_string("CHBCIF\r\n");
1.23 + INV_REG(PORTA, 1 << 2);
1.24 + CLR_REG(DMA_REG(1, DCHxINT), 0b11111111);
1.25 + CLR_REG(DMAIFS, ifs);
1.26 + }
1.27 }
1.28
1.29