1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/examples/vga-pmp/Makefile Mon Oct 22 18:25:46 2018 +0200
1.3 @@ -0,0 +1,33 @@
1.4 +# Makefile - Build the PIC32 deployment payload
1.5 +#
1.6 +# Copyright (C) 2015, 2017, 2018 Paul Boddie <paul@boddie.org.uk>
1.7 +# Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
1.8 +#
1.9 +# This program is free software: you can redistribute it and/or modify
1.10 +# it under the terms of the GNU General Public License as published by
1.11 +# the Free Software Foundation, either version 3 of the License, or
1.12 +# (at your option) any later version.
1.13 +#
1.14 +# This program is distributed in the hope that it will be useful,
1.15 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.17 +# GNU General Public License for more details.
1.18 +#
1.19 +# You should have received a copy of the GNU General Public License
1.20 +# along with this program. If not, see <http://www.gnu.org/licenses/>.
1.21 +
1.22 +include ../../mk/common.mk
1.23 +
1.24 +TARGET = vga.elf
1.25 +DUMP = $(TARGET:.elf=.dump)
1.26 +MAP = $(TARGET:.elf=.map)
1.27 +
1.28 +HEX = $(TARGET:.elf=.hex)
1.29 +SREC = $(TARGET:.elf=.srec)
1.30 +
1.31 +# Ordering of objects is important and cannot be left to replacement rules.
1.32 +
1.33 +SRC = $(START_SRC) main.c $(COMMON_SRC)
1.34 +OBJ = $(START_OBJ) main.o $(COMMON_OBJ)
1.35 +
1.36 +include ../../mk/rules.mk
2.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
2.2 +++ b/examples/vga-pmp/README.txt Mon Oct 22 18:25:46 2018 +0200
2.3 @@ -0,0 +1,111 @@
2.4 +Introduction
2.5 +------------
2.6 +
2.7 +This example demonstrates the generation of an analogue VGA signal from a
2.8 +PIC32 microcontroller using the parallel mode (parallel master port, PMP)
2.9 +peripheral. The result is not entirely satisfactory:
2.10 +
2.11 + * Pixels are very narrow unless buffered using a flip-flop driven by the
2.12 + peripheral, this being a characteristic of the way the peripheral works, it
2.13 + normally being used to drive memory and display controllers.
2.14 +
2.15 + * Introducing a flip-flop means that the final pixel from the pixel data
2.16 + remains asserted and must be reset using a second DMA channel.
2.17 +
2.18 + * Every fourth pixel is wider than the others, this apparently being an
2.19 + artefact of the DMA transfer mechanism.
2.20 +
2.21 +It might be possible introduce some kind of delay to the write strobe (PMWR)
2.22 +and even out the pixel widths, but this has not been investigated.
2.23 +
2.24 +It appears to be the case that the system and peripheral clock frequencies
2.25 +need to be matched. In this example, a frequency of 48MHz has been chosen.
2.26 +
2.27 +Hardware Details
2.28 +================
2.29 +
2.30 +The pin usage of this solution is documented below.
2.31 +
2.32 +PIC32MX270F256B-50I/SP Pin Assignments
2.33 +--------------------------------------
2.34 +
2.35 +MCLR# 1 \/ 28
2.36 + D7/PMD7/RA0 2 27
2.37 + D6/PMD6/RA1 3 26 RB15/U1TX
2.38 + D0/PMD0/RB0 4 25 RB14
2.39 + D1/PMD1/RB1 5 24 RB13/(PMRD)/U1RX
2.40 + D2/PMD2/RB2 6 23
2.41 + PMWR/RB3 7 22 RB11/PGEC2
2.42 + 8 21 RB10/PGEC3
2.43 + RA2 9 20
2.44 + (PMA0)/RA3 10 19
2.45 +HSYNC/OC1/RB4 11 18 RB9/PMD3/D3
2.46 + 12 17 RB8/PMD4/D4
2.47 + 13 16 RB7/PMD5/D5
2.48 +VSYNC/OC2/RB5 14 15
2.49 +
2.50 +Note that RB6 is not available on pin 15 on this device (it is needed for VBUS
2.51 +unlike the MX170 variant).
2.52 +
2.53 +UART Connections
2.54 +----------------
2.55 +
2.56 +UART1 is exposed by the RB13 and RB15 pins.
2.57 +
2.58 +Data Signal Routing
2.59 +-------------------
2.60 +
2.61 +A flip-flop is used to buffer the outputs:
2.62 +
2.63 +Dn -> 74HC273:Dn
2.64 + 74HC273:Qn -> Qn
2.65 +VCC -> 74HC273:MR#
2.66 +PMWR -> 74HC273:CP
2.67 +
2.68 +For two bits of intensity, two bits per colour channel:
2.69 +
2.70 +Q7 -> 2200R -> I
2.71 +Q6 -> 4700R -> I
2.72 +
2.73 +I -> diode -> R
2.74 +I -> diode -> G
2.75 +I -> diode -> B
2.76 +
2.77 +Q5 -> 470R -> R
2.78 +Q4 -> 1000R -> R
2.79 +Q3 -> 470R -> G
2.80 +Q2 -> 1000R -> G
2.81 +Q1 -> 470R -> B
2.82 +Q0 -> 1000R -> B
2.83 +
2.84 +HSYNC -> HS
2.85 +VSYNC -> VS
2.86 +
2.87 +Output Socket Pinout
2.88 +--------------------
2.89 +
2.90 + 5 (GND) 4 (NC) 3 (B) 2 (G) 1 (R)
2.91 +
2.92 + 10 (GND) 9 (NC) 8 (GND) 7 (GND) 6 (GND)
2.93 +
2.94 + 15 (NC) 14 (VS) 13 (HS) 12 (NC) 11 (NC)
2.95 +
2.96 +Output Cable Pinout
2.97 +-------------------
2.98 +
2.99 + 1 (R) 2 (G) 3 (B) 4 (NC) 5 (GND)
2.100 +
2.101 + 6 (GND) 7 (GND) 8 (GND) 9 (NC) 10 (GND)
2.102 +
2.103 + 11 (NC) 12 (NC) 13 (HS) 14 (VS) 15 (NC)
2.104 +
2.105 +References
2.106 +----------
2.107 +
2.108 +https://en.wikipedia.org/wiki/VGA_connector
2.109 +
2.110 +http://papilio.cc/index.php?n=Papilio.VGAWing
2.111 +
2.112 +http://lucidscience.com/pro-vga%20video%20generator-2.aspx
2.113 +
2.114 +https://sites.google.com/site/h2obsession/CBM/C128/rgbi-to-vga
3.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
3.2 +++ b/examples/vga-pmp/devconfig.h Mon Oct 22 18:25:46 2018 +0200
3.3 @@ -0,0 +1,63 @@
3.4 +/*
3.5 + * Device configuration.
3.6 + *
3.7 + * Copyright (C) 2018 Paul Boddie <paul@boddie.org.uk>
3.8 + *
3.9 + * This program is free software: you can redistribute it and/or modify
3.10 + * it under the terms of the GNU General Public License as published by
3.11 + * the Free Software Foundation, either version 3 of the License, or
3.12 + * (at your option) any later version.
3.13 + *
3.14 + * This program is distributed in the hope that it will be useful,
3.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3.17 + * GNU General Public License for more details.
3.18 + *
3.19 + * You should have received a copy of the GNU General Public License
3.20 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
3.21 + */
3.22 +
3.23 +#ifndef __CONFIG_H__
3.24 +#define __CONFIG_H__
3.25 +
3.26 +#include "pic32.h"
3.27 +
3.28 +/*
3.29 +Set the oscillator to be the FRC oscillator with PLL, with peripheral clock
3.30 +divided by 1 (FPBDIV), and FRCDIV+PLL selected (FNOSC).
3.31 +
3.32 +The watchdog timer (FWDTEN) is also disabled.
3.33 +
3.34 +The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with
3.35 +RPB4.
3.36 +*/
3.37 +
3.38 +#define DEVCFG1_CONFIG (DEVCFG1_FWDTEN_OFF | DEVCFG1_FPBDIV_1 | \
3.39 + DEVCFG1_OSCIOFNC_OFF | DEVCFG1_FSOSCEN_OFF | \
3.40 + DEVCFG1_FNOSC_FRCDIV_PLL)
3.41 +
3.42 +/*
3.43 +Set the FRC oscillator PLL function with an input division of 2, an output
3.44 +division of 2, a multiplication of 24, yielding a multiplication of 6.
3.45 +
3.46 +The FRC is apparently at 8MHz but enforces input division of 2 to produce a
3.47 +frequency in the acceptable range from 4MHz to 5MHz for the PLL:
3.48 +
3.49 +8MHz / 2 = 4MHz
3.50 +
3.51 +Multiplication and output division should produce a system clock of 48MHz:
3.52 +
3.53 +4MHz * 24 / 2 = 48MHz
3.54 +*/
3.55 +
3.56 +#define DEVCFG2_CONFIG (DEVCFG2_FPLLODIV_2 | DEVCFG2_FPLLMUL_24 | \
3.57 + DEVCFG2_FPLLIDIV_2)
3.58 +
3.59 +/*
3.60 +The peripheral clock frequency (FPB) will be 48MHz given the above DEVCFG1 and
3.61 +DEVCFG2 settings.
3.62 +*/
3.63 +
3.64 +#define FPB 48000000
3.65 +
3.66 +#endif /* __CONFIG_H__ */
4.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
4.2 +++ b/examples/vga-pmp/main.c Mon Oct 22 18:25:46 2018 +0200
4.3 @@ -0,0 +1,303 @@
4.4 +/*
4.5 + * Generate a VGA signal using a PIC32 microcontroller.
4.6 + *
4.7 + * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk>
4.8 + *
4.9 + * This program is free software: you can redistribute it and/or modify
4.10 + * it under the terms of the GNU General Public License as published by
4.11 + * the Free Software Foundation, either version 3 of the License, or
4.12 + * (at your option) any later version.
4.13 + *
4.14 + * This program is distributed in the hope that it will be useful,
4.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4.17 + * GNU General Public License for more details.
4.18 + *
4.19 + * You should have received a copy of the GNU General Public License
4.20 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
4.21 + */
4.22 +
4.23 +
4.24 +#include "pic32_c.h"
4.25 +#include "init.h"
4.26 +#include "debug.h"
4.27 +#include "main.h"
4.28 +#include "vga.h"
4.29 +
4.30 +
4.31 +
4.32 +/* Display state. */
4.33 +
4.34 +static void (*state_handler)(void);
4.35 +static uint32_t line;
4.36 +
4.37 +/* Pixel data. */
4.38 +
4.39 +static uint8_t linedata[LINE_LENGTH];
4.40 +static const uint8_t zerodata[ZERO_LENGTH] = {0};
4.41 +
4.42 +
4.43 +
4.44 +static void test_linedata(void)
4.45 +{
4.46 + int i;
4.47 +
4.48 + for (i = 0; i < LINE_LENGTH; i++)
4.49 + linedata[i] = (i % 2) ? 0xff : 0x00;
4.50 +}
4.51 +
4.52 +/* Blink an attached LED with delays implemented using a loop. */
4.53 +
4.54 +static void blink(uint32_t delay, uint32_t port, uint32_t pins)
4.55 +{
4.56 + uint32_t counter;
4.57 +
4.58 + /* Clear outputs (LED). */
4.59 +
4.60 + CLR_REG(port, pins);
4.61 +
4.62 + while (1)
4.63 + {
4.64 + counter = delay;
4.65 +
4.66 + while (counter--) __asm__(""); /* retain loop */
4.67 +
4.68 + /* Invert outputs (LED). */
4.69 +
4.70 + INV_REG(port, pins);
4.71 + rbits(PM_REG(0, PMxCON)); uart_write_nl();
4.72 + rhex(PM_REG(0, PMxMODE)); uart_write_nl();
4.73 + }
4.74 +}
4.75 +
4.76 +
4.77 +
4.78 +/* Main program. */
4.79 +
4.80 +void main(void)
4.81 +{
4.82 + line = 0;
4.83 + state_handler = vbp_active;
4.84 + test_linedata();
4.85 +
4.86 + init_memory();
4.87 + init_pins();
4.88 + init_outputs();
4.89 +
4.90 + unlock_config();
4.91 + config_oc();
4.92 + config_uart();
4.93 + lock_config();
4.94 +
4.95 + init_dma();
4.96 + init_pm();
4.97 +
4.98 + /* Configure parallel master mode. */
4.99 +
4.100 + pm_init(0, 0b10);
4.101 + pm_set_output(0, 1, 0);
4.102 + pm_on(0);
4.103 +
4.104 + /* Initiate DMA on the Timer2 interrupt transferring line data to the first
4.105 + byte of PORTB. Do not enable the channel for initiation until the visible
4.106 + region is about to start. */
4.107 +
4.108 + dma_init(0, 3);
4.109 + dma_set_auto_enable(0, 1);
4.110 + dma_set_interrupt(0, T2, 1);
4.111 + dma_set_transfer(0, PHYSICAL((uint32_t) linedata), LINE_LENGTH,
4.112 + HW_PHYSICAL(PM_REG(0, PMxDIN)), 1,
4.113 + LINE_LENGTH);
4.114 + dma_init_interrupt(0, 0b1000, 1, 3);
4.115 +
4.116 + /* Enable DMA on the preceding channel's completion, with this also
4.117 + initiating transfers. This "reset" or "zero" transfer is employed to set
4.118 + the pixel level to black in a connected flip-flop. Without the flip-flop
4.119 + it is superfluous. */
4.120 +
4.121 + dma_init(1, 3);
4.122 + dma_set_chaining(1, dma_chain_previous);
4.123 + dma_set_interrupt(1, DMA0, 1);
4.124 + dma_set_transfer(1, PHYSICAL((uint32_t) zerodata), ZERO_LENGTH,
4.125 + HW_PHYSICAL(PM_REG(0, PMxDIN)), 1,
4.126 + ZERO_LENGTH);
4.127 + dma_set_receive_events(1, 1);
4.128 +
4.129 + /* Configure a timer for the horizontal sync. The timer has no prescaling
4.130 + (0). */
4.131 +
4.132 + timer_init(2, 0, HFREQ_LIMIT);
4.133 + timer_on(2);
4.134 +
4.135 + /* Horizontal sync. */
4.136 +
4.137 + /* Configure output compare in dual compare (continuous output) mode using
4.138 + Timer2 as time base. The interrupt condition drives the first DMA channel
4.139 + and is handled to drive the display state machine. */
4.140 +
4.141 + oc_init(1, 0b101, 2);
4.142 + oc_set_pulse(1, HSYNC_END);
4.143 + oc_set_pulse_end(1, HSYNC_START);
4.144 + oc_init_interrupt(1, 7, 3);
4.145 + oc_on(1);
4.146 +
4.147 + /* Vertical sync. */
4.148 +
4.149 + /* Configure output compare in single compare (output driven low) mode using
4.150 + Timer2 as time base. The unit is enabled later. It is only really used to
4.151 + achieve precisely-timed level transitions in hardware. */
4.152 +
4.153 + oc_init(2, 0b010, 2);
4.154 + oc_set_pulse(2, 0);
4.155 +
4.156 + uart_init(1, 115200);
4.157 + uart_on(1);
4.158 +
4.159 + interrupts_on();
4.160 +
4.161 + blink(3 << 24, PORTA, 1 << 2);
4.162 +}
4.163 +
4.164 +
4.165 +
4.166 +/* Exception and interrupt handlers. */
4.167 +
4.168 +void exception_handler(void)
4.169 +{
4.170 + blink(3 << 12, PORTA, 1 << 2);
4.171 +}
4.172 +
4.173 +void interrupt_handler(void)
4.174 +{
4.175 + uint32_t ifs;
4.176 +
4.177 + /* Check for a OC1 interrupt condition. */
4.178 +
4.179 + ifs = REG(OCIFS) & OC_INT_FLAGS(1, OCxIF);
4.180 +
4.181 + if (ifs)
4.182 + {
4.183 + line += 1;
4.184 + state_handler();
4.185 + CLR_REG(OCIFS, ifs);
4.186 + }
4.187 +}
4.188 +
4.189 +
4.190 +
4.191 +/* Vertical back porch region. */
4.192 +
4.193 +void vbp_active(void)
4.194 +{
4.195 + if (line < VISIBLE_START)
4.196 + return;
4.197 +
4.198 + /* Enter the visible region. */
4.199 +
4.200 + state_handler = visible_active;
4.201 +
4.202 + /* NOTE: Set the line address. */
4.203 +
4.204 + /* Enable the channel for the next line. */
4.205 +
4.206 + dma_on(0);
4.207 +}
4.208 +
4.209 +/* Visible region. */
4.210 +
4.211 +void visible_active(void)
4.212 +{
4.213 + uint32_t ifs;
4.214 +
4.215 + /* Remove any DMA interrupt condition (CHBCIF). */
4.216 +
4.217 + ifs = REG(DMAIFS) & DMA_INT_FLAGS(0, DCHxIF);
4.218 +
4.219 + if (ifs)
4.220 + {
4.221 + CLR_REG(DMA_REG(0, DCHxINT), 0b11111111);
4.222 + CLR_REG(DMAIFS, ifs);
4.223 + }
4.224 +
4.225 + if (line < VFP_START)
4.226 + {
4.227 + /* NOTE: Update the line address and handle wraparound. */
4.228 +
4.229 + return;
4.230 + }
4.231 +
4.232 + /* End the visible region. */
4.233 +
4.234 + state_handler = vfp_active;
4.235 +
4.236 + /* Disable the channel for the next line. */
4.237 +
4.238 + dma_off(0);
4.239 +}
4.240 +
4.241 +/* Vertical front porch region. */
4.242 +
4.243 +void vfp_active(void)
4.244 +{
4.245 + if (line < VSYNC_START)
4.246 + return;
4.247 +
4.248 + /* Enter the vertical sync region. */
4.249 +
4.250 + state_handler = vsync_active;
4.251 +
4.252 + /* Bring vsync low (single compare, output driven low) when the next line
4.253 + starts. */
4.254 +
4.255 + oc_init(2, 0b010, 2);
4.256 + oc_on(2);
4.257 +}
4.258 +
4.259 +/* Vertical sync region. */
4.260 +
4.261 +void vsync_active(void)
4.262 +{
4.263 + if (line < VSYNC_END)
4.264 + return;
4.265 +
4.266 + /* Start again at the top of the display. */
4.267 +
4.268 + line = 0;
4.269 + state_handler = vbp_active;
4.270 +
4.271 + /* Bring vsync high (single compare, output driven high) when the next line
4.272 + starts. */
4.273 +
4.274 + oc_init(2, 0b001, 2);
4.275 + oc_on(2);
4.276 +}
4.277 +
4.278 +
4.279 +
4.280 +/* Peripheral pin configuration. */
4.281 +
4.282 +void config_oc(void)
4.283 +{
4.284 + /* Map OC1 to RPB4. */
4.285 +
4.286 + REG(RPB4R) = 0b0101; /* RPB4R<3:0> = 0101 (OC1) */
4.287 +
4.288 + /* Map OC2 to RPB5. */
4.289 +
4.290 + REG(RPB5R) = 0b0101; /* RPB5R<3:0> = 0101 (OC2) */
4.291 +}
4.292 +
4.293 +void config_uart(void)
4.294 +{
4.295 + /* Map U1RX to RPB13. */
4.296 +
4.297 + REG(U1RXR) = 0b0011; /* U1RXR<3:0> = 0011 (RPB13) */
4.298 +
4.299 + /* Map U1TX to RPB15. */
4.300 +
4.301 + REG(RPB15R) = 0b0001; /* RPB15R<3:0> = 0001 (U1TX) */
4.302 +
4.303 + /* Set RPB13 to input. */
4.304 +
4.305 + SET_REG(TRISB, 1 << 13);
4.306 +}
5.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
5.2 +++ b/examples/vga-pmp/main.h Mon Oct 22 18:25:46 2018 +0200
5.3 @@ -0,0 +1,35 @@
5.4 +/*
5.5 + * Generate a VGA signal using a PIC32 microcontroller.
5.6 + *
5.7 + * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk>
5.8 + *
5.9 + * This program is free software: you can redistribute it and/or modify
5.10 + * it under the terms of the GNU General Public License as published by
5.11 + * the Free Software Foundation, either version 3 of the License, or
5.12 + * (at your option) any later version.
5.13 + *
5.14 + * This program is distributed in the hope that it will be useful,
5.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5.17 + * GNU General Public License for more details.
5.18 + *
5.19 + * You should have received a copy of the GNU General Public License
5.20 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
5.21 + */
5.22 +
5.23 +#ifndef __MAIN_H__
5.24 +#define __MAIN_H__
5.25 +
5.26 +/* Peripheral pin configuration. */
5.27 +
5.28 +void config_oc(void);
5.29 +void config_uart(void);
5.30 +
5.31 +/* Display state handlers. */
5.32 +
5.33 +void vbp_active(void);
5.34 +void visible_active(void);
5.35 +void vfp_active(void);
5.36 +void vsync_active(void);
5.37 +
5.38 +#endif /* __MAIN_H__ */
6.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
6.2 +++ b/examples/vga-pmp/vga.h Mon Oct 22 18:25:46 2018 +0200
6.3 @@ -0,0 +1,55 @@
6.4 +/*
6.5 + * Generate a VGA signal using a PIC32 microcontroller.
6.6 + *
6.7 + * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk>
6.8 + *
6.9 + * This program is free software: you can redistribute it and/or modify
6.10 + * it under the terms of the GNU General Public License as published by
6.11 + * the Free Software Foundation, either version 3 of the License, or
6.12 + * (at your option) any later version.
6.13 + *
6.14 + * This program is distributed in the hope that it will be useful,
6.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6.17 + * GNU General Public License for more details.
6.18 + *
6.19 + * You should have received a copy of the GNU General Public License
6.20 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
6.21 + */
6.22 +
6.23 +#ifndef __VGA_H__
6.24 +#define __VGA_H__
6.25 +
6.26 +#define LINE_LENGTH 160 /* pixels */
6.27 +#define LINE_COUNT 256 /* distinct display lines */
6.28 +
6.29 +#define ZERO_LENGTH 1 /* pixels */
6.30 +
6.31 +/* 48MHz cycle measurements. */
6.32 +
6.33 +#define HFREQ_LIMIT 1286
6.34 +#define HSYNC_START 920
6.35 +#define HSYNC_LIMIT 128
6.36 +#define HSYNC_END (HSYNC_START + HSYNC_LIMIT)
6.37 +
6.38 +/* Horizontal lines, back porch end. */
6.39 +
6.40 +#define VISIBLE_START 70
6.41 +#define VFP_START (VISIBLE_START + 2 * LINE_COUNT)
6.42 +
6.43 +/* Horizontal lines, front porch end. */
6.44 +
6.45 +#define VSYNC_START 620
6.46 +
6.47 +/* Horizontal lines, back porch start. */
6.48 +
6.49 +#define VSYNC_END 622
6.50 +
6.51 +#define SCREEN_BASE 256
6.52 +#define SCREEN_SIZE (40 * 1024)
6.53 +#define SCREEN_LIMIT (SCREEN_BASE + SCREEN_SIZE)
6.54 +
6.55 +#define SCREEN_BASE_KSEG0 (KSEG0_BASE + SCREEN_BASE)
6.56 +#define SCREEN_LIMIT_KSEG0 (KSEG0_BASE + SCREEN_LIMIT)
6.57 +
6.58 +#endif /* __VGA_H__ */