2.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
2.2 +++ b/debug.c Thu Oct 18 18:36:19 2018 +0200
2.3 @@ -0,0 +1,50 @@
2.4 +#include "pic32_c.h"
2.5 +#include "debug.h"
2.6 +
2.7 +/* Value output functions. */
2.8 +
2.9 +void bits(uint32_t reg)
2.10 +{
2.11 + vbits(REG(reg));
2.12 +}
2.13 +
2.14 +void vbits(uint32_t val)
2.15 +{
2.16 + uint32_t mask;
2.17 +
2.18 + for (mask = (1 << 31); mask; mask >>= 1)
2.19 + if (val & mask)
2.20 + uart_write('1');
2.21 + else
2.22 + uart_write('0');
2.23 +
2.24 + uart_write('\r');
2.25 + uart_write('\n');
2.26 +}
2.27 +
2.28 +void vhex(uint32_t val)
2.29 +{
2.30 + uint32_t mask;
2.31 + uint8_t digit, shift;
2.32 +
2.33 + for (mask = (0b1111 << 28), shift = 28; mask; mask >>= 4, shift -= 4)
2.34 + {
2.35 + digit = (val & mask) >> shift;
2.36 + if (digit > 9)
2.37 + uart_write('A' + digit - 10);
2.38 + else
2.39 + uart_write('0' + digit);
2.40 + }
2.41 +
2.42 + uart_write('\r');
2.43 + uart_write('\n');
2.44 +}
2.45 +
2.46 +/* General output functions. */
2.47 +
2.48 +void uart_write(char c)
2.49 +{
2.50 + while (REG(UART_REG(1, UxSTA)) & (1 << 9)); /* UTXBF (buffer full) */
2.51 +
2.52 + REG(UART_REG(1, UxTXREG)) = c;
2.53 +}
4.1 --- a/main.c Thu Oct 18 18:24:48 2018 +0200
4.2 +++ b/main.c Thu Oct 18 18:36:19 2018 +0200
4.3 @@ -1,28 +1,9 @@
4.4 #include "pic32_c.h"
4.5 #include "init.h"
4.6 +#include "debug.h"
4.7
4.8 static const char message[] = "Hello!\r\n";
4.9 -
4.10 -static void uart_write(char c)
4.11 -{
4.12 - while (REG(UART_REG(1, UxSTA)) & (1 << 9)); /* UTXBF (buffer full) */
4.13 -
4.14 - REG(UART_REG(1, UxTXREG)) = c;
4.15 -}
4.16 -
4.17 -static void bits(uint32_t reg)
4.18 -{
4.19 - uint32_t mask;
4.20 -
4.21 - for (mask = (1 << 31); mask; mask >>= 1)
4.22 - if (REG(reg) & mask)
4.23 - uart_write('1');
4.24 - else
4.25 - uart_write('0');
4.26 -
4.27 - uart_write('\r');
4.28 - uart_write('\n');
4.29 -}
4.30 +static int uart_echo = 0;
4.31
4.32 static void blink(uint32_t delay, uint32_t port, uint32_t pins)
4.33 {
4.34 @@ -41,12 +22,6 @@
4.35 /* Invert outputs (LED). */
4.36
4.37 INV_REG(port, pins);
4.38 -
4.39 - bits(DMA_REG(0, DCHxCON));
4.40 - bits(DMA_REG(0, DCHxECON));
4.41 - bits(DMA_REG(0, DCHxINT));
4.42 -
4.43 - /* SET_REG(DMA_REG(0, DCHxECON), 1 << 7); */
4.44 }
4.45 }
4.46
4.47 @@ -60,20 +35,24 @@
4.48 config_uart();
4.49 lock_config();
4.50
4.51 - /* Initiate DMA on UART receive interrupt. */
4.52 + init_dma();
4.53
4.54 - init_dma();
4.55 - dma_init(0, 0, 3);
4.56 - /* dma_set_interrupt(0, U1RX, 1); */
4.57 - dma_set_transfer(0, PHYSICAL(message), sizeof(message) - 1,
4.58 + /* Initiate DMA on UART receive interrupt, raising transfer completion
4.59 + interrupt. Since the channel is not auto-enabled, it must be explicitly
4.60 + enabled upon completion. */
4.61 +
4.62 + dma_init(0, 3);
4.63 + dma_set_interrupt(0, U1RX, 1);
4.64 + dma_set_transfer(0, PHYSICAL((uint32_t) message), sizeof(message) - 1,
4.65 HW_PHYSICAL(UART_REG(1, UxTXREG)), 1,
4.66 1);
4.67 + dma_init_interrupt(0, 0b00001000, 7, 3);
4.68 dma_on(0);
4.69
4.70 - /* Set UART with interrupt. */
4.71 + /* Set UART interrupt priority below CPU priority. */
4.72
4.73 uart_init(1, 115200);
4.74 - uart_init_interrupt(1, UxRIF, 4, 3);
4.75 + uart_init_interrupt(1, UxRIF, 1, 3);
4.76 uart_on(1);
4.77
4.78 interrupts_on();
4.79 @@ -88,9 +67,11 @@
4.80
4.81 void interrupt_handler(void)
4.82 {
4.83 + uint32_t ifs, val;
4.84 +
4.85 /* Check for a UART receive interrupt condition (UxRIF). */
4.86
4.87 - uint32_t ifs = REG(UARTIFS) & UART_INT_FLAGS(1, UxRIF);
4.88 + ifs = REG(UARTIFS) & UART_INT_FLAGS(1, UxRIF);
4.89
4.90 if (ifs)
4.91 {
4.92 @@ -101,8 +82,23 @@
4.93 /* Write the received data back. */
4.94
4.95 while (REG(UART_REG(1, UxSTA)) & 1)
4.96 - uart_write((char) REG(UART_REG(1, UxRXREG)));
4.97 + {
4.98 + val = REG(UART_REG(1, UxRXREG));
4.99 + if (uart_echo)
4.100 + uart_write((char) val);
4.101 + }
4.102 + }
4.103 +
4.104 + /* Check for a DMA interrupt condition (CHBCIF). */
4.105
4.106 + ifs = REG(DMAIFS) & DMA_INT_FLAGS(0, 1);
4.107 +
4.108 + if (ifs)
4.109 + {
4.110 INV_REG(PORTA, 1 << 2);
4.111 + CLR_REG(DMA_REG(0, DCHxINT), 0b11111111);
4.112 + CLR_REG(DMAIFS, ifs);
4.113 +
4.114 + dma_on(0);
4.115 }
4.116 }