1.1 --- a/examples/demo/main.c Sat Oct 20 19:26:44 2018 +0200
1.2 +++ b/examples/demo/main.c Sat Oct 20 21:48:38 2018 +0200
1.3 @@ -69,6 +69,14 @@
1.4
1.5 init_dma();
1.6
1.7 + /* Peripheral relationships:
1.8 +
1.9 + Timer2 -> DMA0: message1 -> U1TXREG
1.10 + \___
1.11 + \
1.12 + Timer3 -> OC1 -> DMA1: message2 -> U1TXREG
1.13 + */
1.14 +
1.15 /* Initiate DMA on the Timer2 interrupt. Since the channel is not
1.16 auto-enabled, it must be explicitly enabled elsewhere (when a UART
1.17 interrupt is handled). */
1.18 @@ -91,11 +99,9 @@
1.19 dma_init_interrupt(1, 0b00001000, 7, 3);
1.20
1.21 /* Configure a timer for the first DMA channel whose interrupt condition
1.22 - drives the transfer but is not handled (having a lower priority than the
1.23 - CPU. */
1.24 + drives the transfer. The interrupt itself does not need to be enabled. */
1.25
1.26 timer_init(2, 0b111, 60000);
1.27 - timer_init_interrupt(2, 1, 3);
1.28 timer_on(2);
1.29
1.30 /* Configure a timer for the output compare unit below. */
1.31 @@ -105,12 +111,11 @@
1.32
1.33 /* Configure output compare in dual compare (continuous output) mode using
1.34 Timer3 as time base. The interrupt condition drives the second DMA
1.35 - channel but is not handled (having a lower priority than the CPU). */
1.36 + channel but does not need to be enabled. */
1.37
1.38 oc_init(1, 0b101, 3);
1.39 oc_set_pulse(1, 10000);
1.40 oc_set_pulse_end(1, 20000);
1.41 - oc_init_interrupt(1, 1, 3);
1.42 oc_on(1);
1.43
1.44 /* Set UART interrupt priority above CPU priority to process events and to