1.1 --- a/examples/vga-timer/main.c Wed Oct 24 13:03:22 2018 +0200
1.2 +++ b/examples/vga-timer/main.c Wed Oct 24 13:21:21 2018 +0200
1.3 @@ -109,7 +109,7 @@
1.4 /* Enable DMA on the zero channel's completion, with the Timer3
1.5 interrupt condition initiating transfers. */
1.6
1.7 - dma_init(0, 3);
1.8 + dma_init(0, 2);
1.9 dma_set_chaining(0, dma_chain_next);
1.10 dma_set_interrupt(0, T3, 1);
1.11 dma_set_transfer(0, PHYSICAL((uint32_t) display_config.screen_start),
1.12 @@ -120,7 +120,7 @@
1.13 /* Enable DMA on the zero channel's completion, with the Timer3
1.14 interrupt condition initiating transfers. */
1.15
1.16 - dma_init(2, 3);
1.17 + dma_init(2, 2);
1.18 dma_set_chaining(2, dma_chain_previous);
1.19 dma_set_interrupt(2, T3, 1);
1.20 dma_set_transfer(2, PHYSICAL((uint32_t) display_config.screen_start +
2.1 --- a/examples/vga-timer/vga.h Wed Oct 24 13:03:22 2018 +0200
2.2 +++ b/examples/vga-timer/vga.h Wed Oct 24 13:21:21 2018 +0200
2.3 @@ -29,7 +29,7 @@
2.4 /* 24MHz cycle measurements. */
2.5
2.6 #define HFREQ_LIMIT 643
2.7 -#define HSYNC_START 504
2.8 +#define HSYNC_START 508
2.9 #define HSYNC_LIMIT 40
2.10 #define HSYNC_END (HSYNC_START + HSYNC_LIMIT)
2.11