1.1 --- a/examples/vga-dual/main.c Wed Oct 24 13:21:21 2018 +0200
1.2 +++ b/examples/vga-dual/main.c Wed Oct 24 15:31:56 2018 +0200
1.3 @@ -118,32 +118,10 @@
1.4 ZERO_LENGTH);
1.5 dma_set_receive_events(2, 1);
1.6
1.7 - /* Configure a timer for the horizontal sync. The timer has no prescaling
1.8 - (0). */
1.9 -
1.10 - timer_init(2, 0, HFREQ_LIMIT);
1.11 - timer_on(2);
1.12 -
1.13 - /* Horizontal sync. */
1.14 -
1.15 - /* Configure output compare in dual compare (continuous output) mode using
1.16 - Timer2 as time base. The interrupt condition drives the first DMA channel
1.17 - and is handled to drive the display state machine. */
1.18 + /* Configure a timer and output compare units for horizontal and vertical
1.19 + sync. */
1.20
1.21 - oc_init(1, 0b101, 2);
1.22 - oc_set_pulse(1, HSYNC_END);
1.23 - oc_set_pulse_end(1, HSYNC_START);
1.24 - oc_init_interrupt(1, 7, 3);
1.25 - oc_on(1);
1.26 -
1.27 - /* Vertical sync. */
1.28 -
1.29 - /* Configure output compare in single compare (output driven low) mode using
1.30 - Timer2 as time base. The unit is enabled later. It is only really used to
1.31 - achieve precisely-timed level transitions in hardware. */
1.32 -
1.33 - oc_init(2, 0b010, 2);
1.34 - oc_set_pulse(2, 0);
1.35 + vga_configure_sync(1, 2, 2);
1.36
1.37 uart_init(1, FPB, 115200);
1.38 uart_on(1);
2.1 --- a/examples/vga-pmp/main.c Wed Oct 24 13:21:21 2018 +0200
2.2 +++ b/examples/vga-pmp/main.c Wed Oct 24 15:31:56 2018 +0200
2.3 @@ -115,32 +115,10 @@
2.4 ZERO_LENGTH);
2.5 dma_set_receive_events(1, 1);
2.6
2.7 - /* Configure a timer for the horizontal sync. The timer has no prescaling
2.8 - (0). */
2.9 -
2.10 - timer_init(2, 0, HFREQ_LIMIT);
2.11 - timer_on(2);
2.12 -
2.13 - /* Horizontal sync. */
2.14 -
2.15 - /* Configure output compare in dual compare (continuous output) mode using
2.16 - Timer2 as time base. The interrupt condition drives the first DMA channel
2.17 - and is handled to drive the display state machine. */
2.18 + /* Configure a timer and output compare units for horizontal and vertical
2.19 + sync. */
2.20
2.21 - oc_init(1, 0b101, 2);
2.22 - oc_set_pulse(1, HSYNC_END);
2.23 - oc_set_pulse_end(1, HSYNC_START);
2.24 - oc_init_interrupt(1, 7, 3);
2.25 - oc_on(1);
2.26 -
2.27 - /* Vertical sync. */
2.28 -
2.29 - /* Configure output compare in single compare (output driven low) mode using
2.30 - Timer2 as time base. The unit is enabled later. It is only really used to
2.31 - achieve precisely-timed level transitions in hardware. */
2.32 -
2.33 - oc_init(2, 0b010, 2);
2.34 - oc_set_pulse(2, 0);
2.35 + vga_configure_sync(1, 2, 2);
2.36
2.37 uart_init(1, FPB, 115200);
2.38 uart_on(1);
3.1 --- a/examples/vga-timer/main.c Wed Oct 24 13:21:21 2018 +0200
3.2 +++ b/examples/vga-timer/main.c Wed Oct 24 15:31:56 2018 +0200
3.3 @@ -140,37 +140,15 @@
3.4 ZERO_LENGTH);
3.5 dma_set_receive_events(3, 1);
3.6
3.7 - /* Configure a timer for the horizontal sync. The timer has no prescaling
3.8 - (0). */
3.9 -
3.10 - timer_init(2, 0, HFREQ_LIMIT);
3.11 - timer_on(2);
3.12 -
3.13 /* Configure a timer for line data transfers. */
3.14
3.15 timer_init(3, 0, 1);
3.16 timer_on(3);
3.17
3.18 - /* Horizontal sync. */
3.19 -
3.20 - /* Configure output compare in dual compare (continuous output) mode using
3.21 - Timer2 as time base. The interrupt condition drives the first DMA channel
3.22 - and is handled to drive the display state machine. */
3.23 + /* Configure a timer and output compare units for horizontal and vertical
3.24 + sync. */
3.25
3.26 - oc_init(1, 0b101, 2);
3.27 - oc_set_pulse(1, HSYNC_END);
3.28 - oc_set_pulse_end(1, HSYNC_START);
3.29 - oc_init_interrupt(1, 7, 3);
3.30 - oc_on(1);
3.31 -
3.32 - /* Vertical sync. */
3.33 -
3.34 - /* Configure output compare in single compare (output driven low) mode using
3.35 - Timer2 as time base. The unit is enabled later. It is only really used to
3.36 - achieve precisely-timed level transitions in hardware. */
3.37 -
3.38 - oc_init(2, 0b010, 2);
3.39 - oc_set_pulse(2, 0);
3.40 + vga_configure_sync(1, 2, 2);
3.41
3.42 uart_init(1, FPB, 115200);
3.43 uart_on(1);
4.1 --- a/examples/vga/main.c Wed Oct 24 13:21:21 2018 +0200
4.2 +++ b/examples/vga/main.c Wed Oct 24 15:31:56 2018 +0200
4.3 @@ -106,32 +106,10 @@
4.4 ZERO_LENGTH);
4.5 dma_set_receive_events(1, 1);
4.6
4.7 - /* Configure a timer for the horizontal sync. The timer has no prescaling
4.8 - (0). */
4.9 -
4.10 - timer_init(2, 0, HFREQ_LIMIT);
4.11 - timer_on(2);
4.12 -
4.13 - /* Horizontal sync. */
4.14 -
4.15 - /* Configure output compare in dual compare (continuous output) mode using
4.16 - Timer2 as time base. The interrupt condition drives the first DMA channel
4.17 - and is handled to drive the display state machine. */
4.18 + /* Configure a timer and output compare units for horizontal and vertical
4.19 + sync. */
4.20
4.21 - oc_init(1, 0b101, 2);
4.22 - oc_set_pulse(1, HSYNC_END);
4.23 - oc_set_pulse_end(1, HSYNC_START);
4.24 - oc_init_interrupt(1, 7, 3);
4.25 - oc_on(1);
4.26 -
4.27 - /* Vertical sync. */
4.28 -
4.29 - /* Configure output compare in single compare (output driven low) mode using
4.30 - Timer2 as time base. The unit is enabled later. It is only really used to
4.31 - achieve precisely-timed level transitions in hardware. */
4.32 -
4.33 - oc_init(2, 0b010, 2);
4.34 - oc_set_pulse(2, 0);
4.35 + vga_configure_sync(1, 2, 2);
4.36
4.37 uart_init(1, FPB, 115200);
4.38 uart_on(1);
5.1 --- a/include/display.h Wed Oct 24 13:21:21 2018 +0200
5.2 +++ b/include/display.h Wed Oct 24 15:31:56 2018 +0200
5.3 @@ -46,6 +46,10 @@
5.4
5.5 int cell_size;
5.6
5.7 + /* Display line positions. */
5.8 +
5.9 + uint32_t hfreq_limit, hsync_start, hsync_end;
5.10 +
5.11 /* Display region scanline positions. */
5.12
5.13 uint32_t visible_start, vfp_start, vsync_start, vsync_end;
6.1 --- a/include/display_config.h Wed Oct 24 13:21:21 2018 +0200
6.2 +++ b/include/display_config.h Wed Oct 24 15:31:56 2018 +0200
6.3 @@ -1,5 +1,6 @@
6.4 /*
6.5 - * Initialisation of application-specific display configuration.
6.6 + * Initialisation of application-specific display configuration. This requires
6.7 + * the prior definition of various display properties.
6.8 *
6.9 * Copyright (C) 2018 Paul Boddie <paul@boddie.org.uk>
6.10 *
6.11 @@ -42,6 +43,9 @@
6.12
6.13 /* Define display region properties. */
6.14
6.15 + .hfreq_limit = HFREQ_LIMIT,
6.16 + .hsync_start = HSYNC_START,
6.17 + .hsync_end = HSYNC_END,
6.18 .visible_start = VISIBLE_START,
6.19 .vfp_start = VFP_START,
6.20 .vsync_start = VSYNC_START,
7.1 --- a/include/vga_display.h Wed Oct 24 13:21:21 2018 +0200
7.2 +++ b/include/vga_display.h Wed Oct 24 15:31:56 2018 +0200
7.3 @@ -68,6 +68,8 @@
7.4 void (*vsync_high)(),
7.5 void (*vsync_low)());
7.6
7.7 +void vga_configure_sync(int hsync_unit, int vsync_unit, int timer);
7.8 +
7.9 /* Interrupt handlers. */
7.10
7.11 void vga_interrupt_handler(void);
8.1 --- a/lib/vga_display.c Wed Oct 24 13:21:21 2018 +0200
8.2 +++ b/lib/vga_display.c Wed Oct 24 15:31:56 2018 +0200
8.3 @@ -18,6 +18,7 @@
8.4 */
8.5
8.6 #include "pic32_c.h"
8.7 +#include "init.h"
8.8 #include "vga_display.h"
8.9
8.10
8.11 @@ -58,6 +59,39 @@
8.12 vga_display.line = 0;
8.13 }
8.14
8.15 +/* Configure a timer and output compare units for horizontal and vertical
8.16 + sync. */
8.17 +
8.18 +void vga_configure_sync(int hsync_unit, int vsync_unit, int timer)
8.19 +{
8.20 + /* Configure a timer for the horizontal sync. The timer has no prescaling
8.21 + (0). */
8.22 +
8.23 + timer_init(timer, 0, vga_display.display_config->hfreq_limit);
8.24 + timer_on(timer);
8.25 +
8.26 + /* Horizontal sync. */
8.27 +
8.28 + /* Configure output compare in dual compare (continuous output) mode using
8.29 + the timer as time base. The interrupt condition drives the first DMA
8.30 + channel and is handled to drive the display state machine. */
8.31 +
8.32 + oc_init(hsync_unit, 0b101, timer);
8.33 + oc_set_pulse(hsync_unit, vga_display.display_config->hsync_end);
8.34 + oc_set_pulse_end(hsync_unit, vga_display.display_config->hsync_start);
8.35 + oc_init_interrupt(hsync_unit, 7, 3);
8.36 + oc_on(hsync_unit);
8.37 +
8.38 + /* Vertical sync. */
8.39 +
8.40 + /* Configure output compare in single compare (output driven low) mode using
8.41 + the timer as time base. The unit is enabled later. It is only really used
8.42 + to achieve precisely-timed level transitions in hardware. */
8.43 +
8.44 + oc_init(vsync_unit, 0b010, timer);
8.45 + oc_set_pulse(vsync_unit, 0);
8.46 +}
8.47 +
8.48
8.49
8.50 /* Interrupt handlers. */