1.1 --- a/init.c Sun Oct 21 19:16:10 2018 +0200
1.2 +++ b/init.c Sun Oct 21 23:25:55 2018 +0200
1.3 @@ -112,13 +112,13 @@
1.4
1.5 void init_dma(void)
1.6 {
1.7 - /* Disable DMA interrupts. */
1.8 + /* Disable DMA interrupts (DMAxIE). */
1.9
1.10 - CLR_REG(DMAIEC, 0b1111 << DMAINTBASE); /* DMA3IE...DMA0IE = 0 */
1.11 + CLR_REG(DMAIEC, 0b1111 << DMAINTBASE);
1.12
1.13 - /* Clear DMA interrupt flags. */
1.14 + /* Clear DMA interrupt flags (DMAxIF). */
1.15
1.16 - CLR_REG(DMAIFS, 0b1111 << DMAINTBASE); /* DMA3IF...DMA0IF = 0 */
1.17 + CLR_REG(DMAIFS, 0b1111 << DMAINTBASE);
1.18
1.19 /* Enable DMA. */
1.20
1.21 @@ -351,6 +351,96 @@
1.22
1.23
1.24
1.25 +/* Parallel mode configuration. */
1.26 +
1.27 +void init_pm(void)
1.28 +{
1.29 + int i;
1.30 +
1.31 + /* Disable PM interrupts (PMxIE). */
1.32 +
1.33 + CLR_REG(PMIEC, 0b11 << PMINTBASE);
1.34 +
1.35 + /* Clear PM interrupt flags (PMxIF). */
1.36 +
1.37 + CLR_REG(PMIFS, 0b11 << PMINTBASE);
1.38 +
1.39 + /* Disable PM for configuration. */
1.40 +
1.41 + for (i = PMMIN; i <= PMMAX; i++)
1.42 + REG(PM_REG(i, PMxCON)) = 0;
1.43 +}
1.44 +
1.45 +/* Configure the parallel mode. */
1.46 +
1.47 +void pm_init(int port, uint8_t mode)
1.48 +{
1.49 + if ((port < PMMIN) || (port > PMMAX))
1.50 + return;
1.51 +
1.52 + REG(PM_REG(port, PMxMODE)) = (mode & 0b11) << 8;
1.53 + REG(PM_REG(port, PMxAEN)) = 0;
1.54 + REG(PM_REG(port, PMxADDR)) = 0;
1.55 + SET_REG(PM_REG(port, PMxCON), 1 << 1); /* WRSP: PMENB active high */
1.56 +}
1.57 +
1.58 +/* Configure output signals. */
1.59 +
1.60 +void pm_set_output(int port, int write_enable, int read_enable)
1.61 +{
1.62 + if ((port < PMMIN) || (port > PMMAX))
1.63 + return;
1.64 +
1.65 + REG(PM_REG(port, PMxCON)) = (write_enable ? (1 << 9) : 0) |
1.66 + (read_enable ? (1 << 8) : 0);
1.67 +}
1.68 +
1.69 +/* Configure interrupts caused by parallel mode. */
1.70 +
1.71 +void pm_init_interrupt(int port, uint8_t pri, uint8_t sub)
1.72 +{
1.73 + if ((port < PMMIN) || (port > PMMAX))
1.74 + return;
1.75 +
1.76 + /* Disable interrupt and clear interrupt flag. */
1.77 +
1.78 + CLR_REG(PMIEC, PM_INT_FLAGS(port, PMxIE));
1.79 + CLR_REG(PMIFS, PM_INT_FLAGS(port, PMxIF));
1.80 +
1.81 + /* Set interrupt priorities. */
1.82 +
1.83 + REG(PM_IPC_REG(port)) = (REG(PM_IPC_REG(port)) &
1.84 + ~(PM_IPC_PRI(port, 7, 3))) |
1.85 + PM_IPC_PRI(port, pri, sub);
1.86 +
1.87 + /* Enable interrupt. */
1.88 +
1.89 + SET_REG(PMIEC, PM_INT_FLAGS(port, PMxIE));
1.90 +}
1.91 +
1.92 +/* Enable parallel mode. */
1.93 +
1.94 +void pm_on(int port)
1.95 +{
1.96 + if ((port < PMMIN) || (port > PMMAX))
1.97 + return;
1.98 +
1.99 + SET_REG(PM_REG(port, PMxCON), 1 << 15);
1.100 +}
1.101 +
1.102 +/* Disable parallel mode. */
1.103 +
1.104 +void pm_off(int port)
1.105 +{
1.106 + if ((port < PMMIN) || (port > PMMAX))
1.107 + return;
1.108 +
1.109 + CLR_REG(PM_REG(port, PMxCON), 1 << 15);
1.110 +}
1.111 +
1.112 +
1.113 +
1.114 +
1.115 /* Timer configuration. */
1.116
1.117 void timer_init(int timer, uint8_t prescale, uint16_t limit)
1.118 @@ -548,6 +638,29 @@
1.119 return (flags & 0b1) << (OCINTBASE + (unit - OCMIN) * OCINTSTEP);
1.120 }
1.121
1.122 +/* Return encoded parallel mode interrupt priorities for combining with a register. */
1.123 +
1.124 +uint32_t PM_IPC_PRI(int port, uint8_t pri, uint8_t sub)
1.125 +{
1.126 + (void) port;
1.127 + return PRI(pri, sub) << PMIPCBASE;
1.128 +}
1.129 +
1.130 +/* Return the parallel mode interrupt priorities register. */
1.131 +
1.132 +uint32_t PM_IPC_REG(int port)
1.133 +{
1.134 + (void) port;
1.135 + return PMIPC;
1.136 +}
1.137 +
1.138 +/* Return the parallel mode interrupt flags for combining with a register. */
1.139 +
1.140 +int PM_INT_FLAGS(int port, uint8_t flags)
1.141 +{
1.142 + return (flags & 0b11) << (PMINTBASE + (port - PMMIN) * PMINTSTEP);
1.143 +}
1.144 +
1.145 /* Return encoded timer interrupt priorities for combining with a register. */
1.146
1.147 uint32_t TIMER_IPC_PRI(int timer, uint8_t pri, uint8_t sub)
2.1 --- a/init.h Sun Oct 21 19:16:10 2018 +0200
2.2 +++ b/init.h Sun Oct 21 23:25:55 2018 +0200
2.3 @@ -111,6 +111,27 @@
2.4
2.5
2.6
2.7 +/* Parallel mode configuration. */
2.8 +
2.9 +void init_pm(void);
2.10 +
2.11 +void pm_init(int port, uint8_t mode);
2.12 +
2.13 +void pm_init_interrupt(int port, uint8_t pri, uint8_t sub);
2.14 +
2.15 +void pm_off(int port);
2.16 +
2.17 +void pm_on(int port);
2.18 +
2.19 +void pm_set_output(int port, int write_enable, int read_enable);
2.20 +
2.21 +int PM_INT_FLAGS(int port, uint8_t flags);
2.22 +
2.23 +uint32_t PM_IPC_PRI(int port, uint8_t pri, uint8_t sub);
2.24 +uint32_t PM_IPC_REG(int port);
2.25 +
2.26 +
2.27 +
2.28 /* Timer configuration. */
2.29
2.30 void timer_init(int timer, uint8_t prescale, uint16_t limit);
3.1 --- a/pic32.h Sun Oct 21 19:16:10 2018 +0200
3.2 +++ b/pic32.h Sun Oct 21 23:25:55 2018 +0200
3.3 @@ -27,14 +27,6 @@
3.4 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet
3.5 */
3.6
3.7 -#define PMCON 0xBF807000
3.8 -#define PMMODE 0xBF807010
3.9 -#define PMADDR 0xBF807020
3.10 -#define PMDOUT 0xBF807030
3.11 -#define PMDIN 0xBF807040
3.12 -#define PMAEN 0xBF807050
3.13 -#define PMSTAT 0xBF807060
3.14 -
3.15 #define OSCCON 0xBF80F000
3.16 #define REFOCON 0xBF80F020
3.17 #define REFOTRIM 0xBF80F030
3.18 @@ -190,6 +182,39 @@
3.19 #define OC5IPC IPC5
3.20 #define OCIPCBASE 16
3.21
3.22 +/* Parallel mode conveniences. */
3.23 +
3.24 +#define PMCON 0xBF807000
3.25 +
3.26 +#define PMxCON 0x00
3.27 +#define PMxMODE 0x10
3.28 +#define PMxADDR 0x20
3.29 +#define PMxDOUT 0x30
3.30 +#define PMxDIN 0x40
3.31 +#define PMxAEN 0x50
3.32 +#define PMxSTAT 0x60
3.33 +
3.34 +#define PMMIN 0
3.35 +#define PMMAX 0
3.36 +#define PMBASE PMCON
3.37 +#define PMSTEP 0
3.38 +
3.39 +#define PMIEC IEC1
3.40 +
3.41 +#define PMxIE 1
3.42 +#define PMxEIE 2
3.43 +
3.44 +#define PMIFS IFS1
3.45 +
3.46 +#define PMxIF 1
3.47 +#define PMxEIF 2
3.48 +
3.49 +#define PMINTBASE 16
3.50 +#define PMINTSTEP 0
3.51 +
3.52 +#define PMIPC IPC8
3.53 +#define PMIPCBASE 24
3.54 +
3.55 /* Timer conveniences. */
3.56
3.57 #define T1CON 0xBF800600
3.58 @@ -281,6 +306,8 @@
3.59 #define OC3 17
3.60 #define OC4 22
3.61 #define OC5 27
3.62 +#define PMP 48
3.63 +#define PMPE 49
3.64 #define T1 4
3.65 #define T2 9
3.66 #define T3 14
4.1 --- a/pic32_c.h Sun Oct 21 19:16:10 2018 +0200
4.2 +++ b/pic32_c.h Sun Oct 21 23:25:55 2018 +0200
4.3 @@ -79,6 +79,11 @@
4.4 return OCBASE + reg + (unit - OCMIN) * OCSTEP;
4.5 }
4.6
4.7 +static inline uint32_t PM_REG(int port, uint32_t reg)
4.8 +{
4.9 + return PMBASE + reg + (port - PMMIN) * PMSTEP;
4.10 +}
4.11 +
4.12 static inline uint32_t TIMER_REG(int timer, uint32_t reg)
4.13 {
4.14 return TIMERBASE + reg + (timer - TIMERMIN) * TIMERSTEP;