1.1 --- a/start.S Sat Oct 20 23:26:38 2018 +0200
1.2 +++ b/start.S Sat Oct 20 23:51:55 2018 +0200
1.3 @@ -27,7 +27,7 @@
1.4
1.5 /*
1.6 Set the oscillator to be the FRC oscillator with PLL, with peripheral clock
1.7 -divided by 2, and FRCDIV+PLL selected.
1.8 +divided by 2 (FPBDIV), and FRCDIV+PLL selected (FNOSC).
1.9
1.10 The watchdog timer (FWDTEN) is also disabled.
1.11
1.12 @@ -36,23 +36,30 @@
1.13 */
1.14
1.15 .section .devcfg1, "a"
1.16 -.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
1.17 +.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 01;
1.18 DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
1.19
1.20 /*
1.21 -Set the FRC oscillator PLL function with an input division of 4, an output
1.22 -division of 2, a multiplication of 24, yielding a multiplication of 3.
1.23 +Set the FRC oscillator PLL function with an input division of 2, an output
1.24 +division of 2, a multiplication of 24, yielding a multiplication of 6.
1.25 +
1.26 +The FRC is apparently at 8MHz but enforces input division of 2 to produce a
1.27 +frequency in the acceptable range from 4MHz to 5MHz for the PLL:
1.28
1.29 -The FRC is apparently at 16MHz and this produces a system clock of 48MHz.
1.30 +8MHz / 2 = 4MHz
1.31 +
1.32 +Multiplication and output division should produce a system clock of 48MHz:
1.33 +
1.34 +4MHz * 24 / 2 = 48MHz
1.35
1.36 The peripheral clock frequency (FPB) will be 24MHz given the above DEVCFG1
1.37 settings.
1.38 */
1.39
1.40 .section .devcfg2, "a"
1.41 -.word 0xfff9fffb /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001;
1.42 +.word 0xfff9fff9 /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001;
1.43 DEVCFG2<6:4> = FPLLMUL<2:0> = 111;
1.44 - DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */
1.45 + DEVCFG2<2:0> = FPLLIDIV<2:0> = 001 */
1.46
1.47 /* The start routine is placed at the boot location. */
1.48