1.1 --- a/docs/wiki/VGA_Signal_Output Fri May 01 17:26:03 2020 +0200
1.2 +++ b/docs/wiki/VGA_Signal_Output Mon Aug 03 00:01:44 2020 +0200
1.3 @@ -25,7 +25,7 @@
1.4 //format=svg
1.5 //transform=notugly
1.6 digraph cpu {
1.7 - node [shape=box,fontsize="13.0",fontname="Helvetica"];
1.8 + node [shape=box,fontsize="13.0",fontname="sans-serif"];
1.9 rankdir=TD;
1.10
1.11 subgraph {
1.12 @@ -86,7 +86,7 @@
1.13 //format=svg
1.14 //transform=notugly
1.15 digraph dma {
1.16 - node [shape=box,fontsize="13.0",fontname="Helvetica"];
1.17 + node [shape=box,fontsize="13.0",fontname="sans-serif"];
1.18 rankdir=TD;
1.19
1.20 subgraph {
1.21 @@ -161,7 +161,7 @@
1.22 //format=svg
1.23 //transform=notugly
1.24 digraph dma {
1.25 - node [shape=box,fontsize="13.0",fontname="Helvetica"];
1.26 + node [shape=box,fontsize="13.0",fontname="sans-serif"];
1.27 rankdir=TD;
1.28
1.29 subgraph {
1.30 @@ -259,7 +259,7 @@
1.31 //format=svg
1.32 //transform=notugly
1.33 digraph dma {
1.34 - node [shape=box,fontsize="13.0",fontname="Helvetica"];
1.35 + node [shape=box,fontsize="13.0",fontname="sans-serif"];
1.36 rankdir=TD;
1.37
1.38 subgraph {
2.1 --- a/docs/wiki/VGA_Signal_Wiring Fri May 01 17:26:03 2020 +0200
2.2 +++ b/docs/wiki/VGA_Signal_Wiring Mon Aug 03 00:01:44 2020 +0200
2.3 @@ -13,8 +13,8 @@
2.4 //format=svg
2.5 //transform=notugly
2.6 digraph routing {
2.7 - graph [ranksep=1.0,style=invis,fontsize="15.0",fontname="Helvetica",splines=ortho];
2.8 - node [shape=box,style=filled,fillcolor=white,fontsize="13.0",fontname="Helvetica"];
2.9 + graph [ranksep=1.0,style=invis,fontsize="15.0",fontname="sans-serif",splines=ortho];
2.10 + node [shape=box,style=filled,fillcolor=white,fontsize="13.0",fontname="sans-serif"];
2.11 rankdir=LR;
2.12
2.13 /* Output pins. */