1.1 --- a/examples/demo/main.c Tue Oct 23 19:09:04 2018 +0200
1.2 +++ b/examples/demo/main.c Tue Oct 23 19:17:34 2018 +0200
1.3 @@ -24,7 +24,21 @@
1.4 #include "main.h"
1.5
1.6 static const char message1[] = "Hello!\r\n";
1.7 -static const char message2[] = "Again!\r\n";
1.8 +
1.9 +#define CELLSIZE4
1.10 +
1.11 +#ifdef CELLSIZE1
1.12 +static const char message2[] = "Adoc gi,hlo\r";
1.13 +static const char message3[] = "n neaan el!\n";
1.14 +#define CELLSIZE 1
1.15 +#endif
1.16 +
1.17 +#ifdef CELLSIZE4
1.18 +static const char message2[] = "And agahell";
1.19 +static const char message3[] = "oncein, o!\r\n";
1.20 +#define CELLSIZE 4
1.21 +#endif
1.22 +
1.23 static int uart_echo;
1.24
1.25
1.26 @@ -71,32 +85,45 @@
1.27
1.28 /* Peripheral relationships:
1.29
1.30 - Timer2 -> DMA0: message1 -> U1TXREG
1.31 + Timer3 -> OC1 -> DMA0: message2 -> U1TXREG
1.32 + ___/
1.33 + /
1.34 + Timer2 -> DMA1: message1 -> U1TXREG
1.35 \___
1.36 \
1.37 - Timer3 -> OC1 -> DMA1: message2 -> U1TXREG
1.38 + Timer3 -> OC1 -> DMA2: message3 -> U1TXREG
1.39 */
1.40
1.41 + /* Enable DMA on the next channel's completion, with OC1 initiating
1.42 + transfers, raising a transfer completion interrupt to be handled. */
1.43 +
1.44 + dma_init(0, 2);
1.45 + dma_set_chaining(0, dma_chain_next);
1.46 + dma_set_interrupt(0, OC1, 1);
1.47 + dma_set_transfer(0, PHYSICAL((uint32_t) message2), sizeof(message2) - 1,
1.48 + HW_PHYSICAL(UART_REG(1, UxTXREG)), 1,
1.49 + CELLSIZE);
1.50 +
1.51 /* Initiate DMA on the Timer2 interrupt. Since the channel is not
1.52 auto-enabled, it must be explicitly enabled elsewhere (when a UART
1.53 interrupt is handled). */
1.54
1.55 - dma_init(0, 3);
1.56 - dma_set_interrupt(0, T2, 1);
1.57 - dma_set_transfer(0, PHYSICAL((uint32_t) message1), sizeof(message1) - 1,
1.58 + dma_init(1, 3);
1.59 + dma_set_interrupt(1, T2, 1);
1.60 + dma_set_transfer(1, PHYSICAL((uint32_t) message1), sizeof(message1) - 1,
1.61 HW_PHYSICAL(UART_REG(1, UxTXREG)), 1,
1.62 1);
1.63
1.64 /* Enable DMA on the preceding channel's completion, with OC1 initiating
1.65 transfers, raising a transfer completion interrupt to be handled. */
1.66
1.67 - dma_init(1, 3);
1.68 - dma_set_chaining(1, dma_chain_previous);
1.69 - dma_set_interrupt(1, OC1, 1);
1.70 - dma_set_transfer(1, PHYSICAL((uint32_t) message2), sizeof(message2) - 1,
1.71 + dma_init(2, 2);
1.72 + dma_set_chaining(2, dma_chain_previous);
1.73 + dma_set_interrupt(2, OC1, 1);
1.74 + dma_set_transfer(2, PHYSICAL((uint32_t) message3), sizeof(message3) - 1,
1.75 HW_PHYSICAL(UART_REG(1, UxTXREG)), 1,
1.76 - 1);
1.77 - dma_init_interrupt(1, 0b00001000, 7, 3);
1.78 + CELLSIZE);
1.79 + dma_init_interrupt(2, 0b00001000, 7, 3);
1.80
1.81 /* Configure a timer for the first DMA channel whose interrupt condition
1.82 drives the transfer. The interrupt itself does not need to be enabled. */
1.83 @@ -165,19 +192,19 @@
1.84 /* Initiate transfer upon receiving a particular character. */
1.85
1.86 if (val == '0')
1.87 - dma_on(0);
1.88 + dma_on(1);
1.89 }
1.90 }
1.91
1.92 /* Check for a DMA interrupt condition (CHBCIF). */
1.93
1.94 - ifs = REG(DMAIFS) & DMA_INT_FLAGS(1, DCHxIF);
1.95 + ifs = REG(DMAIFS) & DMA_INT_FLAGS(2, DCHxIF);
1.96
1.97 if (ifs)
1.98 {
1.99 uart_write_string("CHBCIF\r\n");
1.100 INV_REG(PORTA, 1 << 2);
1.101 - CLR_REG(DMA_REG(1, DCHxINT), 0b11111111);
1.102 + CLR_REG(DMA_REG(2, DCHxINT), 0b11111111);
1.103 CLR_REG(DMAIFS, ifs);
1.104 }
1.105 }