1.1 --- a/init.c Sat Oct 20 23:51:55 2018 +0200
1.2 +++ b/init.c Sun Oct 21 01:43:38 2018 +0200
1.3 @@ -261,6 +261,31 @@
1.4
1.5
1.6
1.7 +/* External interrupt initialisation. */
1.8 +
1.9 +void int_init_interrupt(int int_num, uint8_t pri, uint8_t sub)
1.10 +{
1.11 + if ((int_num < INTMIN) || (int_num > INTMAX))
1.12 + return;
1.13 +
1.14 + /* Disable interrupt and clear interrupt flag. */
1.15 +
1.16 + CLR_REG(INTIEC, INT_INT_FLAGS(int_num, INTxIE));
1.17 + CLR_REG(INTIFS, INT_INT_FLAGS(int_num, INTxIF));
1.18 +
1.19 + /* Set interrupt priorities. */
1.20 +
1.21 + REG(INT_IPC_REG(int_num)) = (REG(INT_IPC_REG(int_num)) &
1.22 + ~(INT_IPC_PRI(int_num, 7, 3))) |
1.23 + INT_IPC_PRI(int_num, pri, sub);
1.24 +
1.25 + /* Enable interrupt. */
1.26 +
1.27 + SET_REG(INTIEC, INT_INT_FLAGS(int_num, INTxIE));
1.28 +}
1.29 +
1.30 +
1.31 +
1.32 /* Output compare configuration. */
1.33
1.34 void oc_init(int unit, uint8_t mode, int timer)
1.35 @@ -463,6 +488,36 @@
1.36 return PRI(pri, sub) << (DCHIPCBASE + (channel - DCHMIN) * DCHIPCSTEP);
1.37 }
1.38
1.39 +/* Return encoded external interrupt priorities for combining with a register. */
1.40 +
1.41 +uint32_t INT_IPC_PRI(int int_num, uint8_t pri, uint8_t sub)
1.42 +{
1.43 + (void) int_num;
1.44 + return PRI(pri, sub) << INTIPCBASE;
1.45 +}
1.46 +
1.47 +/* Return the external interrupt priorities register. */
1.48 +
1.49 +uint32_t INT_IPC_REG(int int_num)
1.50 +{
1.51 + switch (int_num)
1.52 + {
1.53 + case 0: return INT0IPC;
1.54 + case 1: return INT1IPC;
1.55 + case 2: return INT2IPC;
1.56 + case 3: return INT3IPC;
1.57 + case 4: return INT4IPC;
1.58 + default: return 0; /* should not occur */
1.59 + }
1.60 +}
1.61 +
1.62 +/* Return the external interrupt flags for combining with a register. */
1.63 +
1.64 +int INT_INT_FLAGS(int int_num, uint8_t flags)
1.65 +{
1.66 + return (flags & 0b1) << (INTINTBASE + (int_num - INTMIN) * INTINTSTEP);
1.67 +}
1.68 +
1.69 /* Return encoded output compare interrupt priorities for combining with a register. */
1.70
1.71 uint32_t OC_IPC_PRI(int unit, uint8_t pri, uint8_t sub)
2.1 --- a/init.h Sat Oct 20 23:51:55 2018 +0200
2.2 +++ b/init.h Sun Oct 21 01:43:38 2018 +0200
2.3 @@ -81,6 +81,17 @@
2.4
2.5
2.6
2.7 +/* External interrupt configuration. */
2.8 +
2.9 +void int_init_interrupt(int int_num, uint8_t pri, uint8_t sub);
2.10 +
2.11 +int INT_INT_FLAGS(int int_num, uint8_t flags);
2.12 +
2.13 +uint32_t INT_IPC_PRI(int int_num, uint8_t pri, uint8_t sub);
2.14 +uint32_t INT_IPC_REG(int int_num);
2.15 +
2.16 +
2.17 +
2.18 /* Output compare configuration. */
2.19
2.20 void oc_init(int unit, uint8_t mode, int timer);
3.1 --- a/pic32.h Sat Oct 20 23:51:55 2018 +0200
3.2 +++ b/pic32.h Sun Oct 21 01:43:38 2018 +0200
3.3 @@ -41,6 +41,7 @@
3.4 #define CFGCON 0xBF80F200
3.5 #define SYSKEY 0xBF80F230
3.6
3.7 +#define INT2R 0xBF80FA08
3.8 #define U1RXR 0xBF80FA50
3.9
3.10 #define RPA0R 0xBF80FB00
3.11 @@ -62,6 +63,7 @@
3.12 #define IFS1 0xBF881040
3.13 #define IEC0 0xBF881060
3.14 #define IEC1 0xBF881070
3.15 +#define IPC0 0xBF881090
3.16 #define IPC1 0xBF8810A0
3.17 #define IPC2 0xBF8810B0
3.18 #define IPC3 0xBF8810C0
3.19 @@ -130,6 +132,29 @@
3.20 #define DCHIPCBASE 0
3.21 #define DCHIPCSTEP 8
3.22
3.23 +/* External interrupt conveniences. */
3.24 +
3.25 +#define INTMIN 0
3.26 +#define INTMAX 4
3.27 +
3.28 +#define INTIEC IEC0
3.29 +
3.30 +#define INTxIE 1
3.31 +
3.32 +#define INTIFS IFS0
3.33 +
3.34 +#define INTxIF 1
3.35 +
3.36 +#define INTINTBASE 3
3.37 +#define INTINTSTEP 5
3.38 +
3.39 +#define INT0IPC IPC0
3.40 +#define INT1IPC IPC1
3.41 +#define INT2IPC IPC2
3.42 +#define INT3IPC IPC3
3.43 +#define INT4IPC IPC4
3.44 +#define INTIPCBASE 24
3.45 +
3.46 /* Output compare conveniences. */
3.47
3.48 #define OC1CON 0xBF803000
3.49 @@ -246,6 +271,11 @@
3.50 #define DMA1 61
3.51 #define DMA2 62
3.52 #define DMA3 63
3.53 +#define INT0 3
3.54 +#define INT1 8
3.55 +#define INT2 13
3.56 +#define INT3 18
3.57 +#define INT4 23
3.58 #define OC1 7
3.59 #define OC2 12
3.60 #define OC3 17