1.1 --- a/Makefile Wed Oct 17 17:53:08 2018 +0200
1.2 +++ b/Makefile Wed Oct 17 17:56:15 2018 +0200
1.3 @@ -1,4 +1,4 @@
1.4 -# Makefile - Build the IntCondTest payload
1.5 +# Makefile - Build the PIC32 deployment payload
1.6 #
1.7 # Copyright (C) 2015, 2017, 2018 Paul Boddie <paul@boddie.org.uk>
1.8 # Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
1.9 @@ -33,7 +33,7 @@
1.10 -march=mips32
1.11 LDFLAGS = -nostdlib -EL
1.12
1.13 -TARGET = intcond.elf
1.14 +TARGET = payload.elf
1.15 DUMP = $(TARGET:.elf=.dump)
1.16 MAP = $(TARGET:.elf=.map)
1.17 SCRIPT = $(TARGET:.elf=.ld)
1.18 @@ -43,8 +43,8 @@
1.19
1.20 # Ordering of objects is important and cannot be left to replacement rules.
1.21
1.22 -SRC = intcond.S main.c init.c cpu.S
1.23 -OBJ = intcond.o main.o init.o cpu.o
1.24 +SRC = start.S main.c init.c cpu.S
1.25 +OBJ = start.o main.o init.o cpu.o
1.26
1.27 .PHONY: all clean distclean
1.28
2.1 --- a/intcond.S Wed Oct 17 17:53:08 2018 +0200
2.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
2.3 @@ -1,98 +0,0 @@
2.4 -/*
2.5 - * PIC32 microcontroller initialisation code.
2.6 - *
2.7 - * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk>
2.8 - *
2.9 - * This program is free software: you can redistribute it and/or modify
2.10 - * it under the terms of the GNU General Public License as published by
2.11 - * the Free Software Foundation, either version 3 of the License, or
2.12 - * (at your option) any later version.
2.13 - *
2.14 - * This program is distributed in the hope that it will be useful,
2.15 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
2.16 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2.17 - * GNU General Public License for more details.
2.18 - *
2.19 - * You should have received a copy of the GNU General Public License
2.20 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
2.21 - */
2.22 -
2.23 -#include "mips.h"
2.24 -#include "pic32.h"
2.25 -
2.26 -/* Disable JTAG functionality on pins. */
2.27 -
2.28 -.section .devcfg0, "a"
2.29 -.word 0xfffffffb /* DEVCFG0<2> = JTAGEN = 0 */
2.30 -
2.31 -/*
2.32 -Set the oscillator to be the FRC oscillator with PLL, with peripheral clock
2.33 -divided by 2, and FRCDIV+PLL selected.
2.34 -
2.35 -The watchdog timer (FWDTEN) is also disabled.
2.36 -
2.37 -The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with
2.38 -RPB4.
2.39 -*/
2.40 -
2.41 -.section .devcfg1, "a"
2.42 -.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
2.43 - DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
2.44 -
2.45 -/*
2.46 -Set the FRC oscillator PLL function with an input division of 4, an output
2.47 -division of 2, a multiplication of 24, yielding a multiplication of 3.
2.48 -
2.49 -The FRC is apparently at 16MHz and this produces a system clock of 48MHz.
2.50 -
2.51 -The peripheral clock frequency (FPB) will be 24MHz given the above DEVCFG1
2.52 -settings.
2.53 -*/
2.54 -
2.55 -.section .devcfg2, "a"
2.56 -.word 0xfff9fffb /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001;
2.57 - DEVCFG2<6:4> = FPLLMUL<2:0> = 111;
2.58 - DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */
2.59 -
2.60 -/* The start routine is placed at the boot location. */
2.61 -
2.62 -.section .boot, "a"
2.63 -
2.64 -.globl _start
2.65 -.extern main
2.66 -
2.67 -_start:
2.68 - /* Enable caching. */
2.69 -
2.70 - mfc0 $v1, CP0_CONFIG
2.71 - li $t8, ~CONFIG_K0
2.72 - and $v1, $v1, $t8
2.73 - ori $v1, $v1, CONFIG_K0_CACHABLE_NONCOHERENT
2.74 - mtc0 $v1, CP0_CONFIG
2.75 - nop
2.76 -
2.77 - /* Get the RAM size. */
2.78 -
2.79 - la $v1, BMXDRMSZ
2.80 - lw $t0, 0($v1)
2.81 -
2.82 - /* Initialise the stack pointer. */
2.83 -
2.84 - li $v1, KSEG0_BASE
2.85 - addu $sp, $t0, $v1 /* sp = KSEG0_BASE + RAM size */
2.86 -
2.87 - /* Initialise the globals pointer. */
2.88 -
2.89 - lui $gp, %hi(_GLOBAL_OFFSET_TABLE_)
2.90 - ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_)
2.91 -
2.92 - /*
2.93 - Jump to the main program. Since the boot code is separate from the
2.94 - other code, the address cannot be obtained via the GOT.
2.95 - ("relocation truncated to fit: R_MIPS_PC16 against `main'")
2.96 - */
2.97 -
2.98 - lui $t9, %hi(main)
2.99 - ori $t9, $t9, %lo(main)
2.100 - jr $t9
2.101 - nop
3.1 --- a/intcond.ld Wed Oct 17 17:53:08 2018 +0200
3.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
3.3 @@ -1,43 +0,0 @@
3.4 -OUTPUT_ARCH(mips)
3.5 -ENTRY(_start)
3.6 -
3.7 -/* See...
3.8 - * FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX170/270 DEVICES (64 KB RAM, 256 KB FLASH)
3.9 - * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet
3.10 - */
3.11 -
3.12 -MEMORY
3.13 -{
3.14 - kseg1_data_mem (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x10000
3.15 - kseg0_boot_mem (rx) : ORIGIN = 0x9FC00000, LENGTH = 0xBF0
3.16 - kseg0_program_mem (rx) : ORIGIN = 0x9D000000, LENGTH = 0x40000
3.17 - physical_boot_mem (rx) : ORIGIN = 0x1FC00000, LENGTH = 0xBF0
3.18 - physical_program_mem (rx) : ORIGIN = 0x1D000000, LENGTH = 0x40000
3.19 - sfrs : ORIGIN = 0xBF800000, LENGTH = 0x100000
3.20 - configsfrs : ORIGIN = 0xBFC00BF0, LENGTH = 0x10
3.21 - config3 : ORIGIN = 0xBFC00BF0, LENGTH = 0x4
3.22 - config2 : ORIGIN = 0xBFC00BF4, LENGTH = 0x4
3.23 - config1 : ORIGIN = 0xBFC00BF8, LENGTH = 0x4
3.24 - config0 : ORIGIN = 0xBFC00BFC, LENGTH = 0x4
3.25 - physical_config3 : ORIGIN = 0x3FC00BF0, LENGTH = 0x4
3.26 - physical_config2 : ORIGIN = 0x3FC00BF4, LENGTH = 0x4
3.27 - physical_config1 : ORIGIN = 0x3FC00BF8, LENGTH = 0x4
3.28 - physical_config0 : ORIGIN = 0x3FC00BFC, LENGTH = 0x4
3.29 -}
3.30 -
3.31 -SECTIONS
3.32 -{
3.33 - .boot : { *(.boot*) } > kseg0_boot_mem AT > physical_boot_mem
3.34 - .vectors : { *(.vectors*) } > kseg0_program_mem AT > physical_program_mem
3.35 - .text : { *(.text*) } > kseg0_program_mem AT > physical_program_mem
3.36 - .bss : { *(.bss*) } > kseg1_data_mem
3.37 - .rodata : { *(.rodata*) } > kseg0_program_mem AT > physical_program_mem
3.38 - .got : {
3.39 - _gp = ALIGN(16);
3.40 - *(.got*)
3.41 - } > kseg0_program_mem AT > physical_program_mem
3.42 - .devcfg0 : { *(.devcfg0) } > config0 AT > physical_config0
3.43 - .devcfg1 : { *(.devcfg1) } > config1 AT > physical_config1
3.44 - .devcfg2 : { *(.devcfg2) } > config2 AT > physical_config2
3.45 - /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) }
3.46 -}
4.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
4.2 +++ b/payload.ld Wed Oct 17 17:56:15 2018 +0200
4.3 @@ -0,0 +1,43 @@
4.4 +OUTPUT_ARCH(mips)
4.5 +ENTRY(_start)
4.6 +
4.7 +/* See...
4.8 + * FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX170/270 DEVICES (64 KB RAM, 256 KB FLASH)
4.9 + * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet
4.10 + */
4.11 +
4.12 +MEMORY
4.13 +{
4.14 + kseg1_data_mem (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x10000
4.15 + kseg0_boot_mem (rx) : ORIGIN = 0x9FC00000, LENGTH = 0xBF0
4.16 + kseg0_program_mem (rx) : ORIGIN = 0x9D000000, LENGTH = 0x40000
4.17 + physical_boot_mem (rx) : ORIGIN = 0x1FC00000, LENGTH = 0xBF0
4.18 + physical_program_mem (rx) : ORIGIN = 0x1D000000, LENGTH = 0x40000
4.19 + sfrs : ORIGIN = 0xBF800000, LENGTH = 0x100000
4.20 + configsfrs : ORIGIN = 0xBFC00BF0, LENGTH = 0x10
4.21 + config3 : ORIGIN = 0xBFC00BF0, LENGTH = 0x4
4.22 + config2 : ORIGIN = 0xBFC00BF4, LENGTH = 0x4
4.23 + config1 : ORIGIN = 0xBFC00BF8, LENGTH = 0x4
4.24 + config0 : ORIGIN = 0xBFC00BFC, LENGTH = 0x4
4.25 + physical_config3 : ORIGIN = 0x3FC00BF0, LENGTH = 0x4
4.26 + physical_config2 : ORIGIN = 0x3FC00BF4, LENGTH = 0x4
4.27 + physical_config1 : ORIGIN = 0x3FC00BF8, LENGTH = 0x4
4.28 + physical_config0 : ORIGIN = 0x3FC00BFC, LENGTH = 0x4
4.29 +}
4.30 +
4.31 +SECTIONS
4.32 +{
4.33 + .boot : { *(.boot*) } > kseg0_boot_mem AT > physical_boot_mem
4.34 + .vectors : { *(.vectors*) } > kseg0_program_mem AT > physical_program_mem
4.35 + .text : { *(.text*) } > kseg0_program_mem AT > physical_program_mem
4.36 + .bss : { *(.bss*) } > kseg1_data_mem
4.37 + .rodata : { *(.rodata*) } > kseg0_program_mem AT > physical_program_mem
4.38 + .got : {
4.39 + _gp = ALIGN(16);
4.40 + *(.got*)
4.41 + } > kseg0_program_mem AT > physical_program_mem
4.42 + .devcfg0 : { *(.devcfg0) } > config0 AT > physical_config0
4.43 + .devcfg1 : { *(.devcfg1) } > config1 AT > physical_config1
4.44 + .devcfg2 : { *(.devcfg2) } > config2 AT > physical_config2
4.45 + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) }
4.46 +}
5.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
5.2 +++ b/start.S Wed Oct 17 17:56:15 2018 +0200
5.3 @@ -0,0 +1,98 @@
5.4 +/*
5.5 + * PIC32 microcontroller initialisation code.
5.6 + *
5.7 + * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk>
5.8 + *
5.9 + * This program is free software: you can redistribute it and/or modify
5.10 + * it under the terms of the GNU General Public License as published by
5.11 + * the Free Software Foundation, either version 3 of the License, or
5.12 + * (at your option) any later version.
5.13 + *
5.14 + * This program is distributed in the hope that it will be useful,
5.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5.17 + * GNU General Public License for more details.
5.18 + *
5.19 + * You should have received a copy of the GNU General Public License
5.20 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
5.21 + */
5.22 +
5.23 +#include "mips.h"
5.24 +#include "pic32.h"
5.25 +
5.26 +/* Disable JTAG functionality on pins. */
5.27 +
5.28 +.section .devcfg0, "a"
5.29 +.word 0xfffffffb /* DEVCFG0<2> = JTAGEN = 0 */
5.30 +
5.31 +/*
5.32 +Set the oscillator to be the FRC oscillator with PLL, with peripheral clock
5.33 +divided by 2, and FRCDIV+PLL selected.
5.34 +
5.35 +The watchdog timer (FWDTEN) is also disabled.
5.36 +
5.37 +The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with
5.38 +RPB4.
5.39 +*/
5.40 +
5.41 +.section .devcfg1, "a"
5.42 +.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
5.43 + DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
5.44 +
5.45 +/*
5.46 +Set the FRC oscillator PLL function with an input division of 4, an output
5.47 +division of 2, a multiplication of 24, yielding a multiplication of 3.
5.48 +
5.49 +The FRC is apparently at 16MHz and this produces a system clock of 48MHz.
5.50 +
5.51 +The peripheral clock frequency (FPB) will be 24MHz given the above DEVCFG1
5.52 +settings.
5.53 +*/
5.54 +
5.55 +.section .devcfg2, "a"
5.56 +.word 0xfff9fffb /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001;
5.57 + DEVCFG2<6:4> = FPLLMUL<2:0> = 111;
5.58 + DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */
5.59 +
5.60 +/* The start routine is placed at the boot location. */
5.61 +
5.62 +.section .boot, "a"
5.63 +
5.64 +.globl _start
5.65 +.extern main
5.66 +
5.67 +_start:
5.68 + /* Enable caching. */
5.69 +
5.70 + mfc0 $v1, CP0_CONFIG
5.71 + li $t8, ~CONFIG_K0
5.72 + and $v1, $v1, $t8
5.73 + ori $v1, $v1, CONFIG_K0_CACHABLE_NONCOHERENT
5.74 + mtc0 $v1, CP0_CONFIG
5.75 + nop
5.76 +
5.77 + /* Get the RAM size. */
5.78 +
5.79 + la $v1, BMXDRMSZ
5.80 + lw $t0, 0($v1)
5.81 +
5.82 + /* Initialise the stack pointer. */
5.83 +
5.84 + li $v1, KSEG0_BASE
5.85 + addu $sp, $t0, $v1 /* sp = KSEG0_BASE + RAM size */
5.86 +
5.87 + /* Initialise the globals pointer. */
5.88 +
5.89 + lui $gp, %hi(_GLOBAL_OFFSET_TABLE_)
5.90 + ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_)
5.91 +
5.92 + /*
5.93 + Jump to the main program. Since the boot code is separate from the
5.94 + other code, the address cannot be obtained via the GOT.
5.95 + ("relocation truncated to fit: R_MIPS_PC16 against `main'")
5.96 + */
5.97 +
5.98 + lui $t9, %hi(main)
5.99 + ori $t9, $t9, %lo(main)
5.100 + jr $t9
5.101 + nop