1.1 --- a/init.c Sat Oct 20 19:17:46 2018 +0200
1.2 +++ b/init.c Sat Oct 20 19:19:30 2018 +0200
1.3 @@ -139,11 +139,12 @@
1.4 REG(DMA_REG(channel, DCHxINT)) = 0;
1.5 }
1.6
1.7 -/* Set the channel auto-enable mode. */
1.8 +/* Set the channel repeated enable mode, enabling it again when a block transfer
1.9 + completes. The documentation describes this as auto-enable. */
1.10
1.11 -void dma_set_auto_enable(int channel, int auto_enable)
1.12 +void dma_set_auto_enable(int channel, int enable)
1.13 {
1.14 - (auto_enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 4);
1.15 + (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 4);
1.16 }
1.17
1.18 /* Set the channel chaining mode. */
1.19 @@ -170,6 +171,25 @@
1.20 ((enable ? 1 : 0) << 4);
1.21 }
1.22
1.23 +/* Configure only the channel's initiation interrupt status. */
1.24 +
1.25 +void dma_set_interrupt_enable(int channel, int enable)
1.26 +{
1.27 + if ((channel < DCHMIN) || (channel > DCHMAX))
1.28 + return;
1.29 +
1.30 + (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxECON), 1 << 4);
1.31 +}
1.32 +
1.33 +/* Permit the channel to register events while disabled or suspended. A
1.34 + suspended channel is one that is enabled but where the DMA peripheral
1.35 + has been suspended. */
1.36 +
1.37 +void dma_set_receive_events(int channel, int enable)
1.38 +{
1.39 + (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 6);
1.40 +}
1.41 +
1.42 /* Set a channel's transfer parameters. */
1.43
1.44 void dma_set_transfer(int channel,
1.45 @@ -215,16 +235,28 @@
1.46 SET_REG(DMAIEC, DMA_INT_FLAGS(channel, 1));
1.47 }
1.48
1.49 +/* Enable or disable the channel. */
1.50 +
1.51 +void dma_set_enable(int channel, int enable)
1.52 +{
1.53 + if ((channel < DCHMIN) || (channel > DCHMAX))
1.54 + return;
1.55 +
1.56 + (enable ? SET_REG : CLR_REG)(DMA_REG(channel, DCHxCON), 1 << 7);
1.57 +}
1.58 +
1.59 +/* Disable a DMA channel. */
1.60 +
1.61 +void dma_off(int channel)
1.62 +{
1.63 + dma_set_enable(channel, 0);
1.64 +}
1.65 +
1.66 /* Enable a DMA channel. */
1.67
1.68 void dma_on(int channel)
1.69 {
1.70 - if ((channel < DCHMIN) || (channel > DCHMAX))
1.71 - return;
1.72 -
1.73 - /* Enable channel. */
1.74 -
1.75 - SET_REG(DMA_REG(channel, DCHxCON), 1 << 7);
1.76 + dma_set_enable(channel, 1);
1.77 }
1.78
1.79
2.1 --- a/init.h Sat Oct 20 19:17:46 2018 +0200
2.2 +++ b/init.h Sat Oct 20 19:19:30 2018 +0200
2.3 @@ -51,17 +51,25 @@
2.4
2.5 void dma_init(int channel, uint8_t pri);
2.6
2.7 -void dma_set_auto_enable(int channel, int auto_enable);
2.8 +void dma_init_interrupt(int channel, uint8_t conditions,
2.9 + uint8_t pri, uint8_t sub);
2.10 +
2.11 +void dma_off(int channel);
2.12 +
2.13 +void dma_on(int channel);
2.14 +
2.15 +void dma_set_auto_enable(int channel, int enable);
2.16
2.17 void dma_set_chaining(int channel, enum dma_chain chain);
2.18
2.19 -void dma_init_interrupt(int channel, uint8_t conditions,
2.20 - uint8_t pri, uint8_t sub);
2.21 -
2.22 -void dma_on(int channel);
2.23 +void dma_set_enable(int channel, int enable);
2.24
2.25 void dma_set_interrupt(int channel, uint8_t int_num, int enable);
2.26
2.27 +void dma_set_interrupt_enable(int channel, int enable);
2.28 +
2.29 +void dma_set_receive_events(int channel, int enable);
2.30 +
2.31 void dma_set_transfer(int channel,
2.32 uint32_t source_start_address, uint16_t source_size,
2.33 uint32_t destination_start_address, uint16_t destination_size,
2.34 @@ -77,14 +85,14 @@
2.35
2.36 void oc_init(int unit, uint8_t mode, int timer);
2.37
2.38 +void oc_init_interrupt(int unit, uint8_t pri, uint8_t sub);
2.39 +
2.40 +void oc_on(int unit);
2.41 +
2.42 void oc_set_pulse(int unit, uint32_t start);
2.43
2.44 void oc_set_pulse_end(int unit, uint32_t end);
2.45
2.46 -void oc_init_interrupt(int unit, uint8_t pri, uint8_t sub);
2.47 -
2.48 -void oc_on(int unit);
2.49 -
2.50 int OC_INT_FLAGS(int unit, uint8_t flags);
2.51
2.52 uint32_t OC_IPC_PRI(int unit, uint8_t pri, uint8_t sub);