1.1 --- a/pic32.h Fri Oct 19 18:55:36 2018 +0200
1.2 +++ b/pic32.h Sat Oct 20 19:16:03 2018 +0200
1.3 @@ -27,208 +27,214 @@
1.4 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet
1.5 */
1.6
1.7 -#define PMCON 0xBF807000
1.8 -#define PMMODE 0xBF807010
1.9 -#define PMADDR 0xBF807020
1.10 -#define PMDOUT 0xBF807030
1.11 -#define PMDIN 0xBF807040
1.12 -#define PMAEN 0xBF807050
1.13 -#define PMSTAT 0xBF807060
1.14 +#define PMCON 0xBF807000
1.15 +#define PMMODE 0xBF807010
1.16 +#define PMADDR 0xBF807020
1.17 +#define PMDOUT 0xBF807030
1.18 +#define PMDIN 0xBF807040
1.19 +#define PMAEN 0xBF807050
1.20 +#define PMSTAT 0xBF807060
1.21
1.22 -#define OSCCON 0xBF80F000
1.23 -#define REFOCON 0xBF80F020
1.24 -#define REFOTRIM 0xBF80F030
1.25 -#define CFGCON 0xBF80F200
1.26 -#define SYSKEY 0xBF80F230
1.27 +#define OSCCON 0xBF80F000
1.28 +#define REFOCON 0xBF80F020
1.29 +#define REFOTRIM 0xBF80F030
1.30 +#define CFGCON 0xBF80F200
1.31 +#define SYSKEY 0xBF80F230
1.32
1.33 -#define U1RXR 0xBF80FA50
1.34 +#define U1RXR 0xBF80FA50
1.35
1.36 -#define RPA0R 0xBF80FB00
1.37 -#define RPA1R 0xBF80FB04
1.38 -#define RPA2R 0xBF80FB08
1.39 -#define RPA3R 0xBF80FB0C
1.40 -#define RPA4R 0xBF80FB10
1.41 -#define RPB0R 0xBF80FB2C
1.42 -#define RPB1R 0xBF80FB30
1.43 -#define RPB2R 0xBF80FB34
1.44 -#define RPB3R 0xBF80FB38
1.45 -#define RPB4R 0xBF80FB3C
1.46 -#define RPB5R 0xBF80FB40
1.47 -#define RPB10R 0xBF80FB54
1.48 -#define RPB15R 0xBF80FB68
1.49 +#define RPA0R 0xBF80FB00
1.50 +#define RPA1R 0xBF80FB04
1.51 +#define RPA2R 0xBF80FB08
1.52 +#define RPA3R 0xBF80FB0C
1.53 +#define RPA4R 0xBF80FB10
1.54 +#define RPB0R 0xBF80FB2C
1.55 +#define RPB1R 0xBF80FB30
1.56 +#define RPB2R 0xBF80FB34
1.57 +#define RPB3R 0xBF80FB38
1.58 +#define RPB4R 0xBF80FB3C
1.59 +#define RPB5R 0xBF80FB40
1.60 +#define RPB10R 0xBF80FB54
1.61 +#define RPB15R 0xBF80FB68
1.62
1.63 -#define INTCON 0xBF881000
1.64 -#define IFS0 0xBF881030
1.65 -#define IFS1 0xBF881040
1.66 -#define IEC0 0xBF881060
1.67 -#define IEC1 0xBF881070
1.68 -#define IPC1 0xBF8810A0
1.69 -#define IPC2 0xBF8810B0
1.70 -#define IPC3 0xBF8810C0
1.71 -#define IPC4 0xBF8810D0
1.72 -#define IPC5 0xBF8810E0
1.73 -#define IPC6 0xBF8810F0
1.74 -#define IPC7 0xBF881100
1.75 -#define IPC8 0xBF881110
1.76 -#define IPC9 0xBF881120
1.77 -#define IPC10 0xBF881130
1.78 +#define INTCON 0xBF881000
1.79 +#define IFS0 0xBF881030
1.80 +#define IFS1 0xBF881040
1.81 +#define IEC0 0xBF881060
1.82 +#define IEC1 0xBF881070
1.83 +#define IPC1 0xBF8810A0
1.84 +#define IPC2 0xBF8810B0
1.85 +#define IPC3 0xBF8810C0
1.86 +#define IPC4 0xBF8810D0
1.87 +#define IPC5 0xBF8810E0
1.88 +#define IPC6 0xBF8810F0
1.89 +#define IPC7 0xBF881100
1.90 +#define IPC8 0xBF881110
1.91 +#define IPC9 0xBF881120
1.92 +#define IPC10 0xBF881130
1.93
1.94 -#define BMXCON 0xBF882000
1.95 -#define BMXDKPBA 0xBF882010
1.96 -#define BMXDUDBA 0xBF882020
1.97 -#define BMXDUPBA 0xBF882030
1.98 -#define BMXDRMSZ 0xBF882040
1.99 +#define BMXCON 0xBF882000
1.100 +#define BMXDKPBA 0xBF882010
1.101 +#define BMXDUDBA 0xBF882020
1.102 +#define BMXDUPBA 0xBF882030
1.103 +#define BMXDRMSZ 0xBF882040
1.104
1.105 -#define ANSELA 0xBF886000
1.106 -#define TRISA 0xBF886010
1.107 -#define PORTA 0xBF886020
1.108 -#define LATA 0xBF886030
1.109 -#define ODCA 0xBF886040
1.110 -#define ANSELB 0xBF886100
1.111 -#define TRISB 0xBF886110
1.112 -#define PORTB 0xBF886120
1.113 -#define LATB 0xBF886130
1.114 -#define ODCB 0xBF886140
1.115 +#define ANSELA 0xBF886000
1.116 +#define TRISA 0xBF886010
1.117 +#define PORTA 0xBF886020
1.118 +#define LATA 0xBF886030
1.119 +#define ODCA 0xBF886040
1.120 +#define ANSELB 0xBF886100
1.121 +#define TRISB 0xBF886110
1.122 +#define PORTB 0xBF886120
1.123 +#define LATB 0xBF886130
1.124 +#define ODCB 0xBF886140
1.125
1.126 /* DMA conveniences. */
1.127
1.128 -#define DMACON 0xBF883000
1.129 -#define DCH0CON 0xBF883060
1.130 -#define DCH1CON 0xBF883120
1.131 -#define DCH2CON 0xBF8831E0
1.132 -#define DCH3CON 0xBF8832A0
1.133 +#define DMACON 0xBF883000
1.134 +#define DCH0CON 0xBF883060
1.135 +#define DCH1CON 0xBF883120
1.136 +#define DCH2CON 0xBF8831E0
1.137 +#define DCH3CON 0xBF8832A0
1.138
1.139 -#define DCHMIN 0
1.140 -#define DCHMAX 3
1.141 -#define DCHBASE DCH0CON
1.142 -#define DCHSTEP (DCH1CON - DCH0CON)
1.143 +#define DCHMIN 0
1.144 +#define DCHMAX 3
1.145 +#define DCHBASE DCH0CON
1.146 +#define DCHSTEP (DCH1CON - DCH0CON)
1.147
1.148 -#define DCHxCON 0x00
1.149 -#define DCHxECON 0x10
1.150 -#define DCHxINT 0x20
1.151 -#define DCHxSSA 0x30
1.152 -#define DCHxDSA 0x40
1.153 -#define DCHxSSIZ 0x50
1.154 -#define DCHxDSIZ 0x60
1.155 -#define DCHxSPTR 0x70
1.156 -#define DCHxDPTR 0x80
1.157 -#define DCHxCSIZ 0x90
1.158 -#define DCHxCPTR 0xA0
1.159 -#define DCHxDAT 0xB0
1.160 +#define DCHxCON 0x00
1.161 +#define DCHxECON 0x10
1.162 +#define DCHxINT 0x20
1.163 +#define DCHxSSA 0x30
1.164 +#define DCHxDSA 0x40
1.165 +#define DCHxSSIZ 0x50
1.166 +#define DCHxDSIZ 0x60
1.167 +#define DCHxSPTR 0x70
1.168 +#define DCHxDPTR 0x80
1.169 +#define DCHxCSIZ 0x90
1.170 +#define DCHxCPTR 0xA0
1.171 +#define DCHxDAT 0xB0
1.172
1.173 -#define DMAIEC IEC1
1.174 -#define DMAIFS IFS1
1.175 -#define DMAINTBASE 28
1.176 +#define DMAIEC IEC1
1.177 +
1.178 +#define DCHxIE 1
1.179 +
1.180 +#define DMAIFS IFS1
1.181
1.182 -#define DMAIPC IPC10
1.183 -#define DCHIPCBASE 0
1.184 -#define DCHIPCSTEP 8
1.185 +#define DCHxIF 1
1.186 +
1.187 +#define DMAINTBASE 28
1.188 +
1.189 +#define DMAIPC IPC10
1.190 +#define DCHIPCBASE 0
1.191 +#define DCHIPCSTEP 8
1.192
1.193 /* Output compare conveniences. */
1.194
1.195 -#define OC1CON 0xBF803000
1.196 -#define OC2CON 0xBF803200
1.197 -#define OC3CON 0xBF803400
1.198 -#define OC4CON 0xBF803600
1.199 -#define OC5CON 0xBF803800
1.200 +#define OC1CON 0xBF803000
1.201 +#define OC2CON 0xBF803200
1.202 +#define OC3CON 0xBF803400
1.203 +#define OC4CON 0xBF803600
1.204 +#define OC5CON 0xBF803800
1.205
1.206 -#define OCMIN 1
1.207 -#define OCMAX 5
1.208 -#define OCBASE OC1CON
1.209 -#define OCSTEP (OC2CON - OC1CON)
1.210 +#define OCMIN 1
1.211 +#define OCMAX 5
1.212 +#define OCBASE OC1CON
1.213 +#define OCSTEP (OC2CON - OC1CON)
1.214
1.215 -#define OCxCON 0x00
1.216 -#define OCxR 0x10
1.217 -#define OCxRS 0x20
1.218 +#define OCxCON 0x00
1.219 +#define OCxR 0x10
1.220 +#define OCxRS 0x20
1.221
1.222 -#define OCIEC IEC0
1.223 +#define OCIEC IEC0
1.224
1.225 -#define OCxIE 1
1.226 +#define OCxIE 1
1.227
1.228 -#define OCIFS IFS0
1.229 +#define OCIFS IFS0
1.230
1.231 -#define OCxIF 1
1.232 +#define OCxIF 1
1.233
1.234 -#define OCINTBASE 7
1.235 -#define OCINTSTEP 5
1.236 +#define OCINTBASE 7
1.237 +#define OCINTSTEP 5
1.238
1.239 -#define OC1IPC IPC1
1.240 -#define OC2IPC IPC2
1.241 -#define OC3IPC IPC3
1.242 -#define OC4IPC IPC4
1.243 -#define OC5IPC IPC5
1.244 -#define OCIPCBASE 16
1.245 +#define OC1IPC IPC1
1.246 +#define OC2IPC IPC2
1.247 +#define OC3IPC IPC3
1.248 +#define OC4IPC IPC4
1.249 +#define OC5IPC IPC5
1.250 +#define OCIPCBASE 16
1.251
1.252 /* Timer conveniences. */
1.253
1.254 -#define T1CON 0xBF800600
1.255 -#define T2CON 0xBF800800
1.256 -#define T3CON 0xBF800A00
1.257 -#define T4CON 0xBF800C00
1.258 -#define T5CON 0xBF800E00
1.259 +#define T1CON 0xBF800600
1.260 +#define T2CON 0xBF800800
1.261 +#define T3CON 0xBF800A00
1.262 +#define T4CON 0xBF800C00
1.263 +#define T5CON 0xBF800E00
1.264
1.265 -#define TIMERMIN 1
1.266 -#define TIMERMAX 5
1.267 -#define TIMERBASE T1CON
1.268 -#define TIMERSTEP (T2CON - T1CON)
1.269 +#define TIMERMIN 1
1.270 +#define TIMERMAX 5
1.271 +#define TIMERBASE T1CON
1.272 +#define TIMERSTEP (T2CON - T1CON)
1.273
1.274 -#define TxCON 0x00
1.275 -#define TMRx 0x10
1.276 -#define PRx 0x20
1.277 +#define TxCON 0x00
1.278 +#define TMRx 0x10
1.279 +#define PRx 0x20
1.280
1.281 -#define TIMERIEC IEC0
1.282 +#define TIMERIEC IEC0
1.283
1.284 -#define TxIE 1
1.285 +#define TxIE 1
1.286
1.287 -#define TIMERIFS IEC0
1.288 +#define TIMERIFS IEC0
1.289
1.290 -#define TxIF 1
1.291 +#define TxIF 1
1.292
1.293 -#define TIMERINTBASE 4
1.294 -#define TIMERINTSTEP 5
1.295 +#define TIMERINTBASE 4
1.296 +#define TIMERINTSTEP 5
1.297
1.298 -#define TIMER1IPC IPC1
1.299 -#define TIMER2IPC IPC2
1.300 -#define TIMER3IPC IPC3
1.301 -#define TIMER4IPC IPC4
1.302 -#define TIMER5IPC IPC5
1.303 -#define TIMERIPCBASE 0
1.304 +#define TIMER1IPC IPC1
1.305 +#define TIMER2IPC IPC2
1.306 +#define TIMER3IPC IPC3
1.307 +#define TIMER4IPC IPC4
1.308 +#define TIMER5IPC IPC5
1.309 +#define TIMERIPCBASE 0
1.310
1.311 /* UART conveniences. */
1.312
1.313 -#define U1MODE 0xBF806000
1.314 -#define U2MODE 0xBF806200
1.315 +#define U1MODE 0xBF806000
1.316 +#define U2MODE 0xBF806200
1.317
1.318 -#define UARTMIN 1
1.319 -#define UARTMAX 2
1.320 -#define UARTBASE U1MODE
1.321 -#define UARTSTEP (U2MODE - U1MODE)
1.322 +#define UARTMIN 1
1.323 +#define UARTMAX 2
1.324 +#define UARTBASE U1MODE
1.325 +#define UARTSTEP (U2MODE - U1MODE)
1.326
1.327 -#define UxMODE 0x00
1.328 -#define UxSTA 0x10
1.329 -#define UxTXREG 0x20
1.330 -#define UxRXREG 0x30
1.331 -#define UxBRG 0x40
1.332 +#define UxMODE 0x00
1.333 +#define UxSTA 0x10
1.334 +#define UxTXREG 0x20
1.335 +#define UxRXREG 0x30
1.336 +#define UxBRG 0x40
1.337
1.338 -#define UARTIEC IEC1
1.339 +#define UARTIEC IEC1
1.340
1.341 -#define UxEIE 1
1.342 -#define UxRIE 2
1.343 -#define UxTIE 4
1.344 +#define UxEIE 1
1.345 +#define UxRIE 2
1.346 +#define UxTIE 4
1.347
1.348 -#define UARTIFS IFS1
1.349 +#define UARTIFS IFS1
1.350
1.351 -#define UxEIF 1
1.352 -#define UxRIF 2
1.353 -#define UxTIF 4
1.354 +#define UxEIF 1
1.355 +#define UxRIF 2
1.356 +#define UxTIF 4
1.357
1.358 -#define UARTINTBASE 7
1.359 -#define UARTINTSTEP 14
1.360 +#define UARTINTBASE 7
1.361 +#define UARTINTSTEP 14
1.362
1.363 -#define UART1IPC IPC8
1.364 -#define UART1IPCBASE 0
1.365 -#define UART2IPC IPC9
1.366 -#define UART2IPCBASE 8
1.367 +#define UART1IPC IPC8
1.368 +#define UART1IPCBASE 0
1.369 +#define UART2IPC IPC9
1.370 +#define UART2IPCBASE 8
1.371
1.372 /* Interrupt numbers.
1.373 * See...
1.374 @@ -236,24 +242,24 @@
1.375 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet
1.376 */
1.377
1.378 -#define DMA0 60
1.379 -#define DMA1 61
1.380 -#define DMA2 62
1.381 -#define DMA3 63
1.382 -#define OC1 7
1.383 -#define OC2 12
1.384 -#define OC3 17
1.385 -#define OC4 22
1.386 -#define OC5 27
1.387 -#define T1 4
1.388 -#define T2 9
1.389 -#define T3 14
1.390 -#define T4 19
1.391 -#define T5 24
1.392 -#define U1RX 40
1.393 -#define U1TX 41
1.394 -#define U2RX 54
1.395 -#define U2TX 55
1.396 +#define DMA0 60
1.397 +#define DMA1 61
1.398 +#define DMA2 62
1.399 +#define DMA3 63
1.400 +#define OC1 7
1.401 +#define OC2 12
1.402 +#define OC3 17
1.403 +#define OC4 22
1.404 +#define OC5 27
1.405 +#define T1 4
1.406 +#define T2 9
1.407 +#define T3 14
1.408 +#define T4 19
1.409 +#define T5 24
1.410 +#define U1RX 40
1.411 +#define U1TX 41
1.412 +#define U2RX 54
1.413 +#define U2TX 55
1.414
1.415 /* Address modifiers.
1.416 * See...
1.417 @@ -261,8 +267,8 @@
1.418 * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet
1.419 */
1.420
1.421 -#define CLR 0x4
1.422 -#define SET 0x8
1.423 -#define INV 0xC
1.424 +#define CLR 0x4
1.425 +#define SET 0x8
1.426 +#define INV 0xC
1.427
1.428 #endif /* __PIC32_H__ */