1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/examples/demo/devconfig.h Mon Oct 22 18:25:21 2018 +0200
1.3 @@ -0,0 +1,63 @@
1.4 +/*
1.5 + * Device configuration.
1.6 + *
1.7 + * Copyright (C) 2018 Paul Boddie <paul@boddie.org.uk>
1.8 + *
1.9 + * This program is free software: you can redistribute it and/or modify
1.10 + * it under the terms of the GNU General Public License as published by
1.11 + * the Free Software Foundation, either version 3 of the License, or
1.12 + * (at your option) any later version.
1.13 + *
1.14 + * This program is distributed in the hope that it will be useful,
1.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.17 + * GNU General Public License for more details.
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License
1.20 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
1.21 + */
1.22 +
1.23 +#ifndef __CONFIG_H__
1.24 +#define __CONFIG_H__
1.25 +
1.26 +#include "pic32.h"
1.27 +
1.28 +/*
1.29 +Set the oscillator to be the FRC oscillator with PLL, with peripheral clock
1.30 +divided by 2 (FPBDIV), and FRCDIV+PLL selected (FNOSC).
1.31 +
1.32 +The watchdog timer (FWDTEN) is also disabled.
1.33 +
1.34 +The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with
1.35 +RPB4.
1.36 +*/
1.37 +
1.38 +#define DEVCFG1_CONFIG (DEVCFG1_FWDTEN_OFF | DEVCFG1_FPBDIV_2 | \
1.39 + DEVCFG1_OSCIOFNC_OFF | DEVCFG1_FSOSCEN_OFF | \
1.40 + DEVCFG1_FNOSC_FRCDIV_PLL)
1.41 +
1.42 +/*
1.43 +Set the FRC oscillator PLL function with an input division of 2, an output
1.44 +division of 2, a multiplication of 24, yielding a multiplication of 6.
1.45 +
1.46 +The FRC is apparently at 8MHz but enforces input division of 2 to produce a
1.47 +frequency in the acceptable range from 4MHz to 5MHz for the PLL:
1.48 +
1.49 +8MHz / 2 = 4MHz
1.50 +
1.51 +Multiplication and output division should produce a system clock of 48MHz:
1.52 +
1.53 +4MHz * 24 / 2 = 48MHz
1.54 +*/
1.55 +
1.56 +#define DEVCFG2_CONFIG (DEVCFG2_FPLLODIV_2 | DEVCFG2_FPLLMUL_24 | \
1.57 + DEVCFG2_FPLLIDIV_2)
1.58 +
1.59 +/*
1.60 +The peripheral clock frequency (FPB) will be 24MHz given the above DEVCFG1 and
1.61 +DEVCFG2 settings.
1.62 +*/
1.63 +
1.64 +#define FPB 24000000
1.65 +
1.66 +#endif /* __CONFIG_H__ */
2.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
2.2 +++ b/examples/vga/devconfig.h Mon Oct 22 18:25:21 2018 +0200
2.3 @@ -0,0 +1,63 @@
2.4 +/*
2.5 + * Device configuration.
2.6 + *
2.7 + * Copyright (C) 2018 Paul Boddie <paul@boddie.org.uk>
2.8 + *
2.9 + * This program is free software: you can redistribute it and/or modify
2.10 + * it under the terms of the GNU General Public License as published by
2.11 + * the Free Software Foundation, either version 3 of the License, or
2.12 + * (at your option) any later version.
2.13 + *
2.14 + * This program is distributed in the hope that it will be useful,
2.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2.17 + * GNU General Public License for more details.
2.18 + *
2.19 + * You should have received a copy of the GNU General Public License
2.20 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
2.21 + */
2.22 +
2.23 +#ifndef __CONFIG_H__
2.24 +#define __CONFIG_H__
2.25 +
2.26 +#include "pic32.h"
2.27 +
2.28 +/*
2.29 +Set the oscillator to be the FRC oscillator with PLL, with peripheral clock
2.30 +divided by 2 (FPBDIV), and FRCDIV+PLL selected (FNOSC).
2.31 +
2.32 +The watchdog timer (FWDTEN) is also disabled.
2.33 +
2.34 +The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with
2.35 +RPB4.
2.36 +*/
2.37 +
2.38 +#define DEVCFG1_CONFIG (DEVCFG1_FWDTEN_OFF | DEVCFG1_FPBDIV_2 | \
2.39 + DEVCFG1_OSCIOFNC_OFF | DEVCFG1_FSOSCEN_OFF | \
2.40 + DEVCFG1_FNOSC_FRCDIV_PLL)
2.41 +
2.42 +/*
2.43 +Set the FRC oscillator PLL function with an input division of 2, an output
2.44 +division of 2, a multiplication of 24, yielding a multiplication of 6.
2.45 +
2.46 +The FRC is apparently at 8MHz but enforces input division of 2 to produce a
2.47 +frequency in the acceptable range from 4MHz to 5MHz for the PLL:
2.48 +
2.49 +8MHz / 2 = 4MHz
2.50 +
2.51 +Multiplication and output division should produce a system clock of 48MHz:
2.52 +
2.53 +4MHz * 24 / 2 = 48MHz
2.54 +*/
2.55 +
2.56 +#define DEVCFG2_CONFIG (DEVCFG2_FPLLODIV_2 | DEVCFG2_FPLLMUL_24 | \
2.57 + DEVCFG2_FPLLIDIV_2)
2.58 +
2.59 +/*
2.60 +The peripheral clock frequency (FPB) will be 24MHz given the above DEVCFG1 and
2.61 +DEVCFG2 settings.
2.62 +*/
2.63 +
2.64 +#define FPB 24000000
2.65 +
2.66 +#endif /* __CONFIG_H__ */
3.1 --- a/init.c Mon Oct 22 13:24:20 2018 +0200
3.2 +++ b/init.c Mon Oct 22 18:25:21 2018 +0200
3.3 @@ -21,6 +21,10 @@
3.4 #include "pic32_c.h"
3.5 #include "init.h"
3.6
3.7 +/* Application-specific configuration. */
3.8 +
3.9 +#include "devconfig.h"
3.10 +
3.11
3.12
3.13 /* Basic memory and pin initialisation. */
3.14 @@ -491,9 +495,7 @@
3.15
3.16 void uart_init(int uart, uint32_t baudrate)
3.17 {
3.18 - /* NOTE: Configured in the initial payload. */
3.19 -
3.20 - uint32_t FPB = 24000000;
3.21 + /* FPB is configured in the devconfig.h file and set in the start.S file. */
3.22
3.23 if ((uart < UARTMIN) || (uart > UARTMAX))
3.24 return;
4.1 --- a/mk/common.mk Mon Oct 22 13:24:20 2018 +0200
4.2 +++ b/mk/common.mk Mon Oct 22 18:25:21 2018 +0200
4.3 @@ -31,7 +31,7 @@
4.4 -fno-unit-at-a-time -fno-zero-initialized-in-bss \
4.5 -ffreestanding -fno-hosted -fno-builtin \
4.6 -march=mips32 \
4.7 - -I../..
4.8 + -I. -I../..
4.9 LDFLAGS = -nostdlib -EL
4.10
4.11 # Ordering of objects is important and cannot be left to replacement rules.
5.1 --- a/pic32.h Mon Oct 22 13:24:20 2018 +0200
5.2 +++ b/pic32.h Mon Oct 22 18:25:21 2018 +0200
5.3 @@ -84,6 +84,57 @@
5.4 #define LATB 0xBF886130
5.5 #define ODCB 0xBF886140
5.6
5.7 +/* DEVCFG conveniences. */
5.8 +
5.9 +#define DEVCFG1_UNUSED 0xff7fcbd8 /* exclude FWDTWINSZ, WINDIS, WDTPS, FCKSM, POSCMOD, IESO */
5.10 +
5.11 +#define DEVCFG1_FWDTEN_OFF (0 << 23)
5.12 +#define DEVCFG1_FWDTEN_ON (1 << 23)
5.13 +
5.14 +#define DEVCFG1_FPBDIV_1 (0b00 << 12)
5.15 +#define DEVCFG1_FPBDIV_2 (0b01 << 12)
5.16 +#define DEVCFG1_FPBDIV_4 (0b10 << 12)
5.17 +#define DEVCFG1_FPBDIV_8 (0b11 << 12)
5.18 +
5.19 +#define DEVCFG1_OSCIOFNC_ON (0 << 10)
5.20 +#define DEVCFG1_OSCIOFNC_OFF (1 << 10)
5.21 +
5.22 +#define DEVCFG1_FSOSCEN_OFF (0 << 5)
5.23 +#define DEVCFG1_FSOSCEN_ON (1 << 5)
5.24 +
5.25 +#define DEVCFG1_FNOSC_FRC (0b000)
5.26 +#define DEVCFG1_FNOSC_FRCDIV_PLL (0b001)
5.27 +#define DEVCFG1_FNOSC_FRCDIV (0b111)
5.28 +
5.29 +#define DEVCFG2_UNUSED 0xfff8ff88 /* exclude UPLLEN, UPLLIDIV */
5.30 +
5.31 +#define DEVCFG2_FPLLODIV_1 (0b000 << 16)
5.32 +#define DEVCFG2_FPLLODIV_2 (0b001 << 16)
5.33 +#define DEVCFG2_FPLLODIV_4 (0b010 << 16)
5.34 +#define DEVCFG2_FPLLODIV_8 (0b011 << 16)
5.35 +#define DEVCFG2_FPLLODIV_16 (0b100 << 16)
5.36 +#define DEVCFG2_FPLLODIV_32 (0b101 << 16)
5.37 +#define DEVCFG2_FPLLODIV_64 (0b110 << 16)
5.38 +#define DEVCFG2_FPLLODIV_128 (0b111 << 16)
5.39 +
5.40 +#define DEVCFG2_FPLLMUL_15 (0b000 << 4)
5.41 +#define DEVCFG2_FPLLMUL_16 (0b001 << 4)
5.42 +#define DEVCFG2_FPLLMUL_17 (0b010 << 4)
5.43 +#define DEVCFG2_FPLLMUL_18 (0b011 << 4)
5.44 +#define DEVCFG2_FPLLMUL_19 (0b100 << 4)
5.45 +#define DEVCFG2_FPLLMUL_20 (0b101 << 4)
5.46 +#define DEVCFG2_FPLLMUL_21 (0b110 << 4)
5.47 +#define DEVCFG2_FPLLMUL_24 (0b111 << 4)
5.48 +
5.49 +#define DEVCFG2_FPLLIDIV_1 (0b000)
5.50 +#define DEVCFG2_FPLLIDIV_2 (0b001)
5.51 +#define DEVCFG2_FPLLIDIV_3 (0b010)
5.52 +#define DEVCFG2_FPLLIDIV_4 (0b011)
5.53 +#define DEVCFG2_FPLLIDIV_5 (0b100)
5.54 +#define DEVCFG2_FPLLIDIV_6 (0b101)
5.55 +#define DEVCFG2_FPLLIDIV_10 (0b110)
5.56 +#define DEVCFG2_FPLLIDIV_12 (0b111)
5.57 +
5.58 /* DMA conveniences. */
5.59
5.60 #define DMACON 0xBF883000
6.1 --- a/start.S Mon Oct 22 13:24:20 2018 +0200
6.2 +++ b/start.S Mon Oct 22 18:25:21 2018 +0200
6.3 @@ -20,46 +20,24 @@
6.4 #include "mips.h"
6.5 #include "pic32.h"
6.6
6.7 +/* Application-specific configuration. */
6.8 +
6.9 +#include "devconfig.h"
6.10 +
6.11 /* Disable JTAG functionality on pins. */
6.12
6.13 .section .devcfg0, "a"
6.14 .word 0xfffffffb /* DEVCFG0<2> = JTAGEN = 0 */
6.15
6.16 -/*
6.17 -Set the oscillator to be the FRC oscillator with PLL, with peripheral clock
6.18 -divided by 2 (FPBDIV), and FRCDIV+PLL selected (FNOSC).
6.19 -
6.20 -The watchdog timer (FWDTEN) is also disabled.
6.21 -
6.22 -The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with
6.23 -RPB4.
6.24 -*/
6.25 +/* Select oscillator, pin usage, watchdog timer and peripheral clock divider. */
6.26
6.27 .section .devcfg1, "a"
6.28 -.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 01;
6.29 - DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
6.30 -
6.31 -/*
6.32 -Set the FRC oscillator PLL function with an input division of 2, an output
6.33 -division of 2, a multiplication of 24, yielding a multiplication of 6.
6.34 -
6.35 -The FRC is apparently at 8MHz but enforces input division of 2 to produce a
6.36 -frequency in the acceptable range from 4MHz to 5MHz for the PLL:
6.37 +.word (DEVCFG1_UNUSED | DEVCFG1_CONFIG)
6.38
6.39 -8MHz / 2 = 4MHz
6.40 -
6.41 -Multiplication and output division should produce a system clock of 48MHz:
6.42 -
6.43 -4MHz * 24 / 2 = 48MHz
6.44 -
6.45 -The peripheral clock frequency (FPB) will be 24MHz given the above DEVCFG1
6.46 -settings.
6.47 -*/
6.48 +/* Set clock dividers and multiplier. */
6.49
6.50 .section .devcfg2, "a"
6.51 -.word 0xfff9fff9 /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001;
6.52 - DEVCFG2<6:4> = FPLLMUL<2:0> = 111;
6.53 - DEVCFG2<2:0> = FPLLIDIV<2:0> = 001 */
6.54 +.word (DEVCFG2_UNUSED | DEVCFG2_CONFIG)
6.55
6.56 /* The start routine is placed at the boot location. */
6.57