paul@62 | 1 | /* |
paul@62 | 2 | * JZ4780 HDMI peripheral support. |
paul@62 | 3 | * |
paul@62 | 4 | * Copyright (C) 2020 Paul Boddie <paul@boddie.org.uk> |
paul@62 | 5 | * |
paul@62 | 6 | * This program is free software; you can redistribute it and/or |
paul@62 | 7 | * modify it under the terms of the GNU General Public License as |
paul@62 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@62 | 9 | * the License, or (at your option) any later version. |
paul@62 | 10 | * |
paul@62 | 11 | * This program is distributed in the hope that it will be useful, |
paul@62 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@62 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@62 | 14 | * GNU General Public License for more details. |
paul@62 | 15 | * |
paul@62 | 16 | * You should have received a copy of the GNU General Public License |
paul@62 | 17 | * along with this program; if not, write to the Free Software |
paul@62 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@62 | 19 | * Boston, MA 02110-1301, USA |
paul@62 | 20 | */ |
paul@62 | 21 | |
paul@62 | 22 | #include <l4/devices/hdmi-jz4780.h> |
paul@62 | 23 | #include <l4/devices/hw_mmio_register_block.h> |
paul@62 | 24 | |
paul@62 | 25 | #include <l4/sys/irq.h> |
paul@62 | 26 | #include <l4/util/util.h> |
paul@62 | 27 | |
paul@62 | 28 | #include <cstdio> |
paul@62 | 29 | |
paul@62 | 30 | /* |
paul@62 | 31 | I2C pins: |
paul@62 | 32 | |
paul@62 | 33 | HDMI: PF25/SMB4_SDA/DDCSDA, PF24/SMB4_SCK/DDCSCK |
paul@62 | 34 | |
paul@62 | 35 | See: http://mipscreator.imgtec.com/CI20/hardware/board/ci20_jz4780_v2.0.pdf |
paul@62 | 36 | */ |
paul@62 | 37 | |
paul@62 | 38 | enum Regs |
paul@62 | 39 | { |
paul@62 | 40 | // Identification. |
paul@62 | 41 | |
paul@62 | 42 | Design_id = 0x000, // DESIGN_ID |
paul@62 | 43 | Revision_id = 0x001, // REVISION_ID |
paul@62 | 44 | Product_id0 = 0x002, // PRODUCT_ID0 |
paul@62 | 45 | Product_id1 = 0x003, // PRODUCT_ID1 |
paul@62 | 46 | Config_id0 = 0x004, // CONFIG_ID0 |
paul@62 | 47 | Config_id1 = 0x005, // CONFIG_ID1 |
paul@62 | 48 | Config_id2 = 0x006, // CONFIG_ID2 |
paul@62 | 49 | Config_id3 = 0x007, // CONFIG_ID3 |
paul@62 | 50 | |
paul@62 | 51 | // Top-level interrupt control. |
paul@62 | 52 | |
paul@62 | 53 | Int_mask = 0x1ff, // MUTE |
paul@62 | 54 | |
paul@62 | 55 | // Interrupt status and mask for various functions. |
paul@62 | 56 | |
paul@62 | 57 | Fc_int_status0 = 0x100, // FC_STAT0 |
paul@62 | 58 | Fc_int_status1 = 0x101, // FC_STAT1 |
paul@62 | 59 | Fc_int_status2 = 0x102, // FC_STAT2 |
paul@62 | 60 | As_int_status = 0x103, // AS_STAT0 |
paul@62 | 61 | Phy_int_status = 0x104, // PHY_STAT0 |
paul@62 | 62 | Cec_int_status = 0x106, // CEC_STAT0 |
paul@62 | 63 | Vp_int_status = 0x107, // VP_STAT0 |
paul@62 | 64 | Ahb_dma_audio_int_status = 0x109, // AHBDMAAUD_STAT0 |
paul@62 | 65 | |
paul@62 | 66 | Fc_int_mask0 = 0x180, // MUTE_FC_STAT0 |
paul@62 | 67 | Fc_int_mask1 = 0x181, // MUTE_FC_STAT1 |
paul@62 | 68 | Fc_int_mask2 = 0x182, // MUTE_FC_STAT2 |
paul@62 | 69 | As_int_mask = 0x183, // MUTE_AS_STAT0 |
paul@62 | 70 | Phy_int_mask = 0x184, // MUTE_PHY_STAT0 |
paul@62 | 71 | Cec_int_mask = 0x186, // MUTE_CEC_STAT0 |
paul@62 | 72 | Vp_int_mask = 0x187, // MUTE_VP_STAT0 |
paul@62 | 73 | Ahb_dma_audio_int_mask = 0x189, // MUTE_AHBDMAAUD_STAT0 |
paul@62 | 74 | |
paul@62 | 75 | // I2C for E-DDC. |
paul@62 | 76 | |
paul@62 | 77 | I2c_int_status = 0x105, // I2CM_STAT0 |
paul@62 | 78 | I2c_int_mask = 0x185, // MUTE_I2CM_STAT0 |
paul@62 | 79 | |
paul@62 | 80 | I2c_device_address = 0x7e00, // I2CM_SLAVE |
paul@62 | 81 | I2c_register = 0x7e01, // I2CM_ADDRESS |
paul@62 | 82 | I2c_data_out = 0x7e02, // I2CM_DATAO |
paul@62 | 83 | I2c_data_in = 0x7e03, // I2CM_DATAI |
paul@62 | 84 | I2c_operation = 0x7e04, // I2CM_OPERATION |
paul@62 | 85 | I2c_int_config0 = 0x7e05, // I2CM_INT |
paul@62 | 86 | I2c_int_config1 = 0x7e06, // I2CM_CTLINT |
paul@62 | 87 | I2c_divider = 0x7e07, // I2CM_DIV |
paul@62 | 88 | I2c_segment_address = 0x7e08, // I2CM_SEGADDR |
paul@62 | 89 | I2c_software_reset = 0x7e09, // I2CM_SOFTRSTZ |
paul@62 | 90 | I2c_segment_pointer = 0x7e0a, // I2CM_SEGPTR |
paul@62 | 91 | |
paul@62 | 92 | // I2C for PHY. |
paul@62 | 93 | |
paul@62 | 94 | I2c_phy_int_status = 0x108, // I2CMPHY_STAT0 |
paul@62 | 95 | I2c_phy_int_mask = 0x188, // MUTE_I2CMPHY_STAT0 |
paul@62 | 96 | |
paul@62 | 97 | I2c_phy_int_config0 = 0x3027, // PHY_I2CM_INT_ADDR |
paul@62 | 98 | I2c_phy_int_config1 = 0x3028, // PHY_I2CM_CTLINT_ADDR |
paul@62 | 99 | }; |
paul@62 | 100 | |
paul@62 | 101 | // Identification values. |
paul@62 | 102 | |
paul@62 | 103 | enum Product_id_values : unsigned |
paul@62 | 104 | { |
paul@62 | 105 | Product_id0_transmitter = 0xa0, // PRODUCT_ID0_HDMI_TX |
paul@62 | 106 | |
paul@62 | 107 | Product_id1_hdcp = 0xc0, // PRODUCT_ID1_HDCP |
paul@62 | 108 | Product_id1_receiver = 0x02, // PRODUCT_ID1_HDMI_RX |
paul@62 | 109 | Product_id1_transmitter = 0x01, // PRODUCT_ID1_HDMI_TX |
paul@62 | 110 | }; |
paul@62 | 111 | |
paul@62 | 112 | // Configuration values. |
paul@62 | 113 | |
paul@62 | 114 | enum Config_id_values : unsigned |
paul@62 | 115 | { |
paul@62 | 116 | Config_id0_i2s = 0x10, // CONFIG0_I2S |
paul@62 | 117 | Config_id0_cec = 0x02, // CONFIG0_CEC |
paul@62 | 118 | |
paul@62 | 119 | Config_id1_ahb = 0x01, // CONFIG1_AHB |
paul@62 | 120 | |
paul@62 | 121 | Config2_dwc_hdmi_tx_phy = 0x00, // DWC_HDMI_TX_PHY |
paul@62 | 122 | Config2_dwc_mhl_phy_heac = 0xb2, // DWC_MHL_PHY_HEAC |
paul@62 | 123 | Config2_dwc_mhl_phy = 0xc2, // DWC_MHL_PHY |
paul@62 | 124 | Config2_dwc_hdmi_3d_tx_phy_heac = 0xe2, // DWC_HDMI_3D_TX_PHY_HEAC |
paul@62 | 125 | Config2_dwc_hdmi_3d_tx_phy = 0xf2, // DWC_HDMI_3D_TX_PHY |
paul@62 | 126 | Config2_dwc_hdmi20_tx_phy = 0xf3, // DWC_HDMI20_TX_PHY |
paul@62 | 127 | Config2_vendor_phy = 0xfe, // VENDOR_PHY |
paul@62 | 128 | |
paul@62 | 129 | Config_id3_ahb_audio_dma = 0x02, // CONFIG3_AHBAUDDMA |
paul@62 | 130 | Config_id3_gp_audio = 0x01, // CONFIG3_GPAUD |
paul@62 | 131 | }; |
paul@62 | 132 | |
paul@62 | 133 | // Status and mask bits. |
paul@62 | 134 | |
paul@62 | 135 | enum Int_mask_bits : unsigned |
paul@62 | 136 | { |
paul@62 | 137 | Int_mask_wakeup = 0x2, |
paul@62 | 138 | Int_mask_all = 0x1, |
paul@62 | 139 | }; |
paul@62 | 140 | |
paul@62 | 141 | enum I2c_int_status_bits : unsigned |
paul@62 | 142 | { |
paul@62 | 143 | I2c_int_status_done = 0x2, |
paul@62 | 144 | I2c_int_status_error = 0x1, |
paul@62 | 145 | }; |
paul@62 | 146 | |
paul@62 | 147 | // I2C operation bits. |
paul@62 | 148 | |
paul@62 | 149 | enum I2c_operation_bits : unsigned |
paul@62 | 150 | { |
paul@62 | 151 | I2c_operation_write = 0x10, |
paul@62 | 152 | I2c_operation_segment_read = 0x2, |
paul@62 | 153 | I2c_operation_read = 0x1, |
paul@62 | 154 | }; |
paul@62 | 155 | |
paul@62 | 156 | // Interrupt configuration bits. |
paul@62 | 157 | |
paul@62 | 158 | enum I2c_int_config0_bits : unsigned |
paul@62 | 159 | { |
paul@62 | 160 | I2c_int_config_done_polarity = 0x8, |
paul@62 | 161 | I2c_int_config_done_mask = 0x4, |
paul@62 | 162 | }; |
paul@62 | 163 | |
paul@62 | 164 | enum I2c_int_config1_bits : unsigned |
paul@62 | 165 | { |
paul@62 | 166 | I2c_int_config_nack_polarity = 0x80, |
paul@62 | 167 | I2c_int_config_nack_mask = 0x40, |
paul@62 | 168 | I2c_int_config_arb_polarity = 0x8, |
paul@62 | 169 | I2c_int_config_arb_mask = 0x4, |
paul@62 | 170 | }; |
paul@62 | 171 | |
paul@62 | 172 | |
paul@62 | 173 | |
paul@62 | 174 | // Initialise the HDMI peripheral. |
paul@62 | 175 | |
paul@62 | 176 | Hdmi_jz4780_chip::Hdmi_jz4780_chip(l4_addr_t start, l4_addr_t end, |
paul@62 | 177 | l4_cap_idx_t irq) |
paul@62 | 178 | : _start(start), _end(end), _irq(irq) |
paul@62 | 179 | { |
paul@62 | 180 | // 8-bit registers with 2-bit address shifting. |
paul@62 | 181 | |
paul@62 | 182 | _regs = new Hw::Mmio_register_block<8>(start, 2); |
paul@62 | 183 | |
paul@62 | 184 | _segment_read = false; |
paul@62 | 185 | _device_register = 0; |
paul@62 | 186 | |
paul@62 | 187 | get_identification(); |
paul@62 | 188 | int_init(); |
paul@62 | 189 | i2c_init(); |
paul@62 | 190 | } |
paul@62 | 191 | |
paul@62 | 192 | void Hdmi_jz4780_chip::get_identification() |
paul@62 | 193 | { |
paul@62 | 194 | _version = (_regs[Design_id] << 8) | _regs[Revision_id]; |
paul@62 | 195 | } |
paul@62 | 196 | |
paul@62 | 197 | void Hdmi_jz4780_chip::get_version(uint8_t *major, uint16_t *minor) |
paul@62 | 198 | { |
paul@62 | 199 | *major = _version >> 12; |
paul@62 | 200 | *minor = _version & 0xfff; |
paul@62 | 201 | } |
paul@62 | 202 | |
paul@62 | 203 | void Hdmi_jz4780_chip::int_init() |
paul@62 | 204 | { |
paul@62 | 205 | // Disable interrupts. |
paul@62 | 206 | |
paul@62 | 207 | _regs[Int_mask] = _regs[Int_mask] | (Int_mask_wakeup | Int_mask_all); |
paul@62 | 208 | |
paul@62 | 209 | // Mask all interrupts. |
paul@62 | 210 | |
paul@62 | 211 | _regs[Fc_int_mask0] = 0xff; |
paul@62 | 212 | _regs[Fc_int_mask1] = 0xff; |
paul@62 | 213 | _regs[Fc_int_mask2] = 0xff; |
paul@62 | 214 | _regs[As_int_mask] = 0xff; |
paul@62 | 215 | _regs[Phy_int_mask] = 0xff; |
paul@62 | 216 | _regs[I2c_int_mask] = 0xff; |
paul@62 | 217 | _regs[Cec_int_mask] = 0xff; |
paul@62 | 218 | _regs[Vp_int_mask] = 0xff; |
paul@62 | 219 | _regs[I2c_phy_int_mask] = 0xff; |
paul@62 | 220 | _regs[Ahb_dma_audio_int_mask] = 0xff; |
paul@62 | 221 | |
paul@62 | 222 | // Enable interrupts. |
paul@62 | 223 | |
paul@62 | 224 | _regs[Int_mask] = _regs[Int_mask] & ~(Int_mask_wakeup | Int_mask_all); |
paul@62 | 225 | } |
paul@62 | 226 | |
paul@62 | 227 | void Hdmi_jz4780_chip::i2c_init() |
paul@62 | 228 | { |
paul@62 | 229 | // Set PHY interrupt priorities. |
paul@62 | 230 | |
paul@62 | 231 | _regs[I2c_phy_int_config0] = I2c_int_config_done_polarity; |
paul@62 | 232 | _regs[I2c_phy_int_config1] = I2c_int_config_nack_polarity | |
paul@62 | 233 | I2c_int_config_arb_polarity; |
paul@62 | 234 | |
paul@62 | 235 | // Software reset. |
paul@62 | 236 | |
paul@62 | 237 | _regs[I2c_software_reset] = 0; |
paul@62 | 238 | |
paul@62 | 239 | // Standard mode (100kHz). |
paul@62 | 240 | |
paul@62 | 241 | _regs[I2c_divider] = 0; |
paul@62 | 242 | |
paul@62 | 243 | // Set interrupt polarities. |
paul@62 | 244 | |
paul@62 | 245 | _regs[I2c_int_config0] = I2c_int_config_done_polarity; |
paul@62 | 246 | _regs[I2c_int_config1] = I2c_int_config_nack_polarity | |
paul@62 | 247 | I2c_int_config_arb_polarity; |
paul@62 | 248 | |
paul@62 | 249 | // Clear and mask/mute interrupts. |
paul@62 | 250 | |
paul@62 | 251 | _regs[I2c_int_status] = I2c_int_status_done | I2c_int_status_error; |
paul@62 | 252 | _regs[I2c_int_mask] = I2c_int_status_done | I2c_int_status_error; |
paul@62 | 253 | } |
paul@62 | 254 | |
paul@62 | 255 | long Hdmi_jz4780_chip::i2c_wait() |
paul@62 | 256 | { |
paul@62 | 257 | long err; |
paul@62 | 258 | |
paul@62 | 259 | // Wait for around 1s. |
paul@62 | 260 | |
paul@62 | 261 | l4_msgtag_t tag = l4_irq_receive(_irq, L4_IPC_NEVER); |
paul@62 | 262 | |
paul@62 | 263 | err = l4_ipc_error(tag, l4_utcb()); |
paul@62 | 264 | if (err) |
paul@62 | 265 | return err; |
paul@62 | 266 | |
paul@62 | 267 | // Test for an error condition. |
paul@62 | 268 | |
paul@62 | 269 | if (_regs[I2c_int_status] & I2c_int_status_error) |
paul@62 | 270 | return -L4_EIO; |
paul@62 | 271 | |
paul@62 | 272 | _regs[I2c_int_status] = _regs[I2c_int_status] | I2c_int_status_done; |
paul@62 | 273 | |
paul@62 | 274 | return L4_EOK; |
paul@62 | 275 | } |
paul@62 | 276 | |
paul@62 | 277 | int Hdmi_jz4780_chip::i2c_read(uint8_t *buf, unsigned int length) |
paul@62 | 278 | { |
paul@62 | 279 | unsigned int i; |
paul@62 | 280 | long err; |
paul@62 | 281 | |
paul@62 | 282 | // Clear interrupts. |
paul@62 | 283 | |
paul@62 | 284 | _regs[I2c_int_mask] = 0; |
paul@62 | 285 | |
paul@62 | 286 | for (i = 0; i < length; i++) |
paul@62 | 287 | { |
paul@62 | 288 | // Increment the device register. |
paul@62 | 289 | |
paul@62 | 290 | _regs[I2c_register] = _device_register++; |
paul@62 | 291 | _regs[I2c_operation] = _segment_read ? I2c_operation_segment_read |
paul@62 | 292 | : I2c_operation_read; |
paul@62 | 293 | |
paul@62 | 294 | // Wait and then read. |
paul@62 | 295 | |
paul@62 | 296 | err = i2c_wait(); |
paul@62 | 297 | if (err) |
paul@62 | 298 | break; |
paul@62 | 299 | |
paul@62 | 300 | buf[i] = _regs[I2c_data_in]; |
paul@62 | 301 | } |
paul@62 | 302 | |
paul@62 | 303 | // Mask interrupts again. |
paul@62 | 304 | |
paul@62 | 305 | _regs[I2c_int_mask] = I2c_int_status_done | I2c_int_status_error; |
paul@62 | 306 | |
paul@62 | 307 | return i; |
paul@62 | 308 | } |
paul@62 | 309 | |
paul@62 | 310 | void Hdmi_jz4780_chip::i2c_set_address(uint8_t address) |
paul@62 | 311 | { |
paul@62 | 312 | _regs[I2c_device_address] = address; |
paul@62 | 313 | _segment_read = false; |
paul@62 | 314 | i2c_set_register(0); |
paul@62 | 315 | } |
paul@62 | 316 | |
paul@62 | 317 | void Hdmi_jz4780_chip::i2c_set_segment(uint8_t segment) |
paul@62 | 318 | { |
paul@62 | 319 | _regs[I2c_segment_address] = 0x30; |
paul@62 | 320 | _regs[I2c_segment_pointer] = segment; |
paul@62 | 321 | _segment_read = true; |
paul@62 | 322 | i2c_set_register(0); |
paul@62 | 323 | } |
paul@62 | 324 | |
paul@62 | 325 | void Hdmi_jz4780_chip::i2c_set_register(uint8_t device_register) |
paul@62 | 326 | { |
paul@62 | 327 | _device_register = device_register; |
paul@62 | 328 | } |
paul@62 | 329 | |
paul@62 | 330 | |
paul@62 | 331 | |
paul@62 | 332 | // C language interface functions. |
paul@62 | 333 | |
paul@62 | 334 | void *jz4780_hdmi_init(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq) |
paul@62 | 335 | { |
paul@62 | 336 | return (void *) new Hdmi_jz4780_chip(start, end, irq); |
paul@62 | 337 | } |
paul@62 | 338 | |
paul@62 | 339 | void jz4780_hdmi_get_version(void *hdmi, uint8_t *major, uint16_t *minor) |
paul@62 | 340 | { |
paul@62 | 341 | static_cast<Hdmi_jz4780_chip *>(hdmi)->get_version(major, minor); |
paul@62 | 342 | } |
paul@62 | 343 | |
paul@62 | 344 | int jz4780_hdmi_i2c_read(void *hdmi, uint8_t *buf, unsigned int length) |
paul@62 | 345 | { |
paul@62 | 346 | return static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_read(buf, length); |
paul@62 | 347 | } |
paul@62 | 348 | |
paul@62 | 349 | void jz4780_hdmi_i2c_set_address(void *hdmi, uint8_t address) |
paul@62 | 350 | { |
paul@62 | 351 | static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_address(address); |
paul@62 | 352 | } |
paul@62 | 353 | |
paul@62 | 354 | void jz4780_hdmi_i2c_set_segment(void *hdmi, uint8_t segment) |
paul@62 | 355 | { |
paul@62 | 356 | static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_segment(segment); |
paul@62 | 357 | } |
paul@62 | 358 | |
paul@62 | 359 | void jz4780_hdmi_i2c_set_register(void *hdmi, uint8_t device_register) |
paul@62 | 360 | { |
paul@62 | 361 | static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_register(device_register); |
paul@62 | 362 | } |