paul@114 | 1 | /* |
paul@114 | 2 | * I2C support for the JZ4730. |
paul@114 | 3 | * |
paul@131 | 4 | * Copyright (C) 2017, 2018, 2020, 2021 Paul Boddie <paul@boddie.org.uk> |
paul@114 | 5 | * |
paul@114 | 6 | * This program is free software; you can redistribute it and/or |
paul@114 | 7 | * modify it under the terms of the GNU General Public License as |
paul@114 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@114 | 9 | * the License, or (at your option) any later version. |
paul@114 | 10 | * |
paul@114 | 11 | * This program is distributed in the hope that it will be useful, |
paul@114 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@114 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@114 | 14 | * GNU General Public License for more details. |
paul@114 | 15 | * |
paul@114 | 16 | * You should have received a copy of the GNU General Public License |
paul@114 | 17 | * along with this program; if not, write to the Free Software |
paul@114 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@114 | 19 | * Boston, MA 02110-1301, USA |
paul@114 | 20 | */ |
paul@114 | 21 | |
paul@114 | 22 | #include <l4/devices/i2c-jz4730.h> |
paul@114 | 23 | #include <l4/devices/hw_mmio_register_block.h> |
paul@114 | 24 | |
paul@114 | 25 | #include <l4/sys/icu.h> |
paul@118 | 26 | #include <l4/sys/ipc.h> |
paul@118 | 27 | #include <l4/sys/irq.h> |
paul@114 | 28 | #include <l4/util/util.h> |
paul@114 | 29 | |
paul@114 | 30 | #include <cstdio> |
paul@114 | 31 | |
paul@114 | 32 | /* |
paul@114 | 33 | I2C pins are dedicated to I2C only and are not GPIO-controlled: |
paul@114 | 34 | |
paul@114 | 35 | I2C0: Y4/SMB0_SDA, V5/SMB0_SCK |
paul@114 | 36 | |
paul@114 | 37 | Note that there is effectively only one I2C channel. |
paul@114 | 38 | */ |
paul@114 | 39 | |
paul@114 | 40 | enum Regs |
paul@114 | 41 | { |
paul@114 | 42 | I2c_data = 0x000, // I2CDR |
paul@114 | 43 | I2c_control = 0x004, // I2CCR |
paul@114 | 44 | I2c_status = 0x008, // I2CSR |
paul@114 | 45 | I2c_clock = 0x00c, // I2CGR |
paul@114 | 46 | }; |
paul@114 | 47 | |
paul@114 | 48 | enum I2c_control_bits : unsigned |
paul@114 | 49 | { |
paul@114 | 50 | I2c_control_enable_irq = 0x10, // IEN |
paul@114 | 51 | I2c_control_start = 0x08, // STA |
paul@114 | 52 | I2c_control_stop = 0x04, // STO |
paul@114 | 53 | I2c_control_nack = 0x02, // AC |
paul@114 | 54 | I2c_control_enable = 0x01, // I2CE |
paul@114 | 55 | }; |
paul@114 | 56 | |
paul@114 | 57 | enum I2c_status_bits : unsigned |
paul@114 | 58 | { |
paul@114 | 59 | I2c_status_buffer_nempty = 0x10, // STX |
paul@114 | 60 | I2c_status_busy = 0x08, // BUSY |
paul@114 | 61 | I2c_status_transmit_end = 0x04, // TEND |
paul@114 | 62 | I2c_status_data_valid = 0x02, // DRF |
paul@114 | 63 | I2c_status_nack = 0x01, // ACKF |
paul@114 | 64 | }; |
paul@114 | 65 | |
paul@114 | 66 | enum I2c_clock_values : unsigned |
paul@114 | 67 | { |
paul@114 | 68 | I2c_clock_max = 0xffff, |
paul@114 | 69 | I2c_clock_min = 0, |
paul@114 | 70 | }; |
paul@114 | 71 | |
paul@114 | 72 | |
paul@114 | 73 | |
paul@114 | 74 | // Initialise a channel. |
paul@114 | 75 | |
paul@114 | 76 | I2c_jz4730_channel::I2c_jz4730_channel(l4_addr_t start, |
paul@114 | 77 | Cpm_jz4730_chip *cpm, |
paul@118 | 78 | uint32_t frequency, |
paul@118 | 79 | l4_cap_idx_t irq) |
paul@118 | 80 | : _cpm(cpm), _frequency(frequency), _irq(irq) |
paul@114 | 81 | { |
paul@114 | 82 | _regs = new Hw::Mmio_register_block<32>(start); |
paul@114 | 83 | } |
paul@114 | 84 | |
paul@114 | 85 | // Enable the channel. |
paul@114 | 86 | |
paul@114 | 87 | void |
paul@114 | 88 | I2c_jz4730_channel::enable() |
paul@114 | 89 | { |
paul@114 | 90 | // Make sure that the I2C clock is available. |
paul@114 | 91 | |
paul@128 | 92 | _cpm->start_clock(Clock_i2c); |
paul@114 | 93 | |
paul@114 | 94 | // Set the bus clock frequency. |
paul@114 | 95 | |
paul@114 | 96 | set_frequency(); |
paul@114 | 97 | |
paul@114 | 98 | // Enable the channel and interrupts. |
paul@114 | 99 | |
paul@114 | 100 | _regs[I2c_control] = I2c_control_enable | I2c_control_enable_irq; |
paul@114 | 101 | while (!(_regs[I2c_control] & I2c_control_enable)); |
paul@114 | 102 | } |
paul@114 | 103 | |
paul@114 | 104 | // Disable the channel. |
paul@114 | 105 | |
paul@114 | 106 | void |
paul@114 | 107 | I2c_jz4730_channel::disable() |
paul@114 | 108 | { |
paul@114 | 109 | _regs[I2c_control] = 0; |
paul@114 | 110 | while (_regs[I2c_control] & I2c_control_enable); |
paul@114 | 111 | } |
paul@114 | 112 | |
paul@114 | 113 | // Set the frequency-related peripheral parameters. |
paul@114 | 114 | |
paul@114 | 115 | void |
paul@114 | 116 | I2c_jz4730_channel::set_frequency() |
paul@114 | 117 | { |
paul@114 | 118 | // The APB clock (PCLK) is used to drive I2C transfers. Its value must be |
paul@114 | 119 | // obtained from the CPM unit and is scaled to kHz in order to keep the |
paul@114 | 120 | // numbers easily representable, as is the bus frequency. |
paul@114 | 121 | |
paul@114 | 122 | uint32_t pclk = _cpm->get_pclock_frequency() / 1000; |
paul@114 | 123 | uint32_t i2c_clk = _frequency / 1000; |
paul@114 | 124 | uint32_t division = pclk / (16 * i2c_clk); |
paul@114 | 125 | |
paul@114 | 126 | if (division > I2c_clock_min) |
paul@114 | 127 | { |
paul@114 | 128 | division -= 1; |
paul@114 | 129 | if (division > I2c_clock_max) |
paul@114 | 130 | division = I2c_clock_max; |
paul@114 | 131 | } |
paul@114 | 132 | |
paul@114 | 133 | _regs[I2c_clock] = division; |
paul@114 | 134 | } |
paul@114 | 135 | |
paul@136 | 136 | // State machine controller. |
paul@114 | 137 | |
paul@136 | 138 | void |
paul@136 | 139 | I2c_jz4730_channel::communicate() |
paul@114 | 140 | { |
paul@136 | 141 | enum I2c_jz4730_state state = I2c_jz4730_pre_start; |
paul@136 | 142 | _limit = 10; |
paul@118 | 143 | |
paul@118 | 144 | do |
paul@118 | 145 | { |
paul@136 | 146 | wait_for_irq(1000); |
paul@136 | 147 | |
paul@136 | 148 | switch (state) |
paul@136 | 149 | { |
paul@136 | 150 | case I2c_jz4730_pre_start: |
paul@136 | 151 | state = pre_start(); |
paul@136 | 152 | break; |
paul@136 | 153 | |
paul@136 | 154 | case I2c_jz4730_start_read: |
paul@136 | 155 | state = start_read(); |
paul@136 | 156 | break; |
paul@136 | 157 | |
paul@136 | 158 | case I2c_jz4730_perform_read: |
paul@136 | 159 | state = perform_read(); |
paul@136 | 160 | break; |
paul@136 | 161 | |
paul@136 | 162 | case I2c_jz4730_perform_write: |
paul@136 | 163 | state = perform_write(); |
paul@136 | 164 | break; |
paul@136 | 165 | |
paul@136 | 166 | case I2c_jz4730_stop_write: |
paul@136 | 167 | state = stop_write(); |
paul@136 | 168 | break; |
paul@136 | 169 | |
paul@136 | 170 | default: |
paul@136 | 171 | break; |
paul@136 | 172 | } |
paul@118 | 173 | } |
paul@136 | 174 | while (state != I2c_jz4730_end); |
paul@136 | 175 | } |
paul@136 | 176 | |
paul@136 | 177 | // State machine implementation handlers. |
paul@136 | 178 | |
paul@136 | 179 | // Assert not busy state, issue start, present the address on the bus. |
paul@136 | 180 | |
paul@136 | 181 | enum I2c_jz4730_state |
paul@136 | 182 | I2c_jz4730_channel::pre_start() |
paul@136 | 183 | { |
paul@136 | 184 | // Wait again if busy up to the limit. |
paul@136 | 185 | |
paul@136 | 186 | if (busy()) |
paul@136 | 187 | { |
paul@136 | 188 | if (!(--_limit)) |
paul@136 | 189 | return I2c_jz4730_end; |
paul@136 | 190 | else |
paul@136 | 191 | return I2c_jz4730_pre_start; |
paul@136 | 192 | } |
paul@136 | 193 | |
paul@136 | 194 | // Use a longer time limit in subsequent activities. |
paul@136 | 195 | |
paul@136 | 196 | _limit = 1000; |
paul@136 | 197 | |
paul@136 | 198 | // Start, send address, proceed to the operation. |
paul@118 | 199 | |
paul@114 | 200 | start(); |
paul@114 | 201 | |
paul@136 | 202 | _regs[I2c_data] = (_address << 1) | (_read ? 1 : 0); |
paul@114 | 203 | |
paul@114 | 204 | send_next(); |
paul@114 | 205 | |
paul@136 | 206 | return _read ? I2c_jz4730_start_read : I2c_jz4730_perform_write; |
paul@136 | 207 | } |
paul@136 | 208 | |
paul@136 | 209 | // Wait for an opportunity to begin reading. |
paul@136 | 210 | |
paul@136 | 211 | enum I2c_jz4730_state |
paul@136 | 212 | I2c_jz4730_channel::start_read() |
paul@136 | 213 | { |
paul@136 | 214 | // Wait again if not ready to read. |
paul@136 | 215 | |
paul@136 | 216 | if (transferring() || (!data_valid() && !nack())) |
paul@136 | 217 | return I2c_jz4730_start_read; |
paul@136 | 218 | |
paul@136 | 219 | return I2c_jz4730_perform_read; |
paul@136 | 220 | } |
paul@136 | 221 | |
paul@136 | 222 | // Attempt to read from the device. |
paul@136 | 223 | |
paul@136 | 224 | enum I2c_jz4730_state |
paul@136 | 225 | I2c_jz4730_channel::perform_read() |
paul@136 | 226 | { |
paul@136 | 227 | // Wait again if no available data. |
paul@136 | 228 | |
paul@136 | 229 | if (!data_valid() && !nack()) |
paul@136 | 230 | { |
paul@136 | 231 | if (!(--_limit)) |
paul@136 | 232 | { |
paul@136 | 233 | stop(); |
paul@136 | 234 | return I2c_jz4730_end; |
paul@136 | 235 | } |
paul@136 | 236 | else |
paul@136 | 237 | return I2c_jz4730_perform_read; |
paul@136 | 238 | } |
paul@136 | 239 | |
paul@136 | 240 | // Stop if NACK received. |
paul@136 | 241 | |
paul@136 | 242 | if (nack()) |
paul@136 | 243 | { |
paul@136 | 244 | stop(); |
paul@136 | 245 | return I2c_jz4730_end; |
paul@136 | 246 | } |
paul@136 | 247 | |
paul@136 | 248 | // Signal last byte if appropriate. |
paul@136 | 249 | |
paul@136 | 250 | if ((!_nread && (_length == 1)) || (_nread == _length - 2)) |
paul@136 | 251 | signal_last(); |
paul@136 | 252 | |
paul@136 | 253 | // Store and solicit data. |
paul@136 | 254 | |
paul@136 | 255 | _buf[_nread++] = _regs[I2c_data]; |
paul@136 | 256 | clear_next(); |
paul@136 | 257 | |
paul@136 | 258 | // Stop if all data received. |
paul@136 | 259 | |
paul@136 | 260 | if (_nread >= _length) |
paul@136 | 261 | { |
paul@136 | 262 | stop(); |
paul@136 | 263 | return I2c_jz4730_end; |
paul@136 | 264 | } |
paul@136 | 265 | |
paul@136 | 266 | // Wait for more data otherwise. |
paul@136 | 267 | |
paul@136 | 268 | _limit = 1000; |
paul@136 | 269 | return I2c_jz4730_perform_read; |
paul@136 | 270 | } |
paul@136 | 271 | |
paul@136 | 272 | // Attempt to write to the device. |
paul@136 | 273 | |
paul@136 | 274 | enum I2c_jz4730_state |
paul@136 | 275 | I2c_jz4730_channel::perform_write() |
paul@136 | 276 | { |
paul@136 | 277 | // Wait for data (address or previous data) to be sent. |
paul@136 | 278 | |
paul@136 | 279 | if (data_valid() && !nack()) |
paul@136 | 280 | { |
paul@136 | 281 | if (!(--_limit)) |
paul@136 | 282 | { |
paul@136 | 283 | stop(); |
paul@136 | 284 | return I2c_jz4730_end; |
paul@136 | 285 | } |
paul@136 | 286 | else |
paul@136 | 287 | return I2c_jz4730_perform_write; |
paul@136 | 288 | } |
paul@136 | 289 | |
paul@136 | 290 | // Stop if all data written or NACK received. |
paul@136 | 291 | |
paul@136 | 292 | if ((_nwritten >= _length) || nack()) |
paul@136 | 293 | { |
paul@136 | 294 | stop(); |
paul@136 | 295 | _limit = 1000; |
paul@136 | 296 | return I2c_jz4730_stop_write; |
paul@136 | 297 | } |
paul@136 | 298 | |
paul@136 | 299 | // Write more data. |
paul@136 | 300 | |
paul@136 | 301 | _regs[I2c_data] = _buf[_nwritten++]; |
paul@136 | 302 | send_next(); |
paul@136 | 303 | |
paul@136 | 304 | // Wait for the data to be sent. |
paul@136 | 305 | |
paul@136 | 306 | _limit = 1000; |
paul@136 | 307 | return I2c_jz4730_perform_write; |
paul@136 | 308 | } |
paul@136 | 309 | |
paul@136 | 310 | // Terminate the write transaction. |
paul@136 | 311 | |
paul@136 | 312 | enum I2c_jz4730_state |
paul@136 | 313 | I2c_jz4730_channel::stop_write() |
paul@136 | 314 | { |
paul@136 | 315 | if (!transferred()) |
paul@136 | 316 | { |
paul@136 | 317 | if (--_limit) |
paul@136 | 318 | return I2c_jz4730_stop_write; |
paul@136 | 319 | } |
paul@136 | 320 | |
paul@136 | 321 | return I2c_jz4730_end; |
paul@118 | 322 | } |
paul@118 | 323 | |
paul@118 | 324 | // Wait up to the given timeout (in microseconds) for an interrupt request, |
paul@118 | 325 | // returning true if one was delivered. |
paul@118 | 326 | |
paul@118 | 327 | bool |
paul@118 | 328 | I2c_jz4730_channel::wait_for_irq(unsigned int timeout) |
paul@118 | 329 | { |
paul@118 | 330 | return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, l4util_micros2l4to(timeout)))); |
paul@114 | 331 | } |
paul@114 | 332 | |
paul@114 | 333 | // Read data from the bus. |
paul@114 | 334 | |
paul@114 | 335 | unsigned int |
paul@114 | 336 | I2c_jz4730_channel::read(uint8_t address, uint8_t buf[], unsigned int length) |
paul@114 | 337 | { |
paul@136 | 338 | _nread = 0; |
paul@136 | 339 | _length = length; |
paul@136 | 340 | _address = address; |
paul@136 | 341 | _buf = &buf[0]; |
paul@136 | 342 | _read = true; |
paul@131 | 343 | |
paul@136 | 344 | communicate(); |
paul@118 | 345 | |
paul@136 | 346 | return _nread; |
paul@114 | 347 | } |
paul@114 | 348 | |
paul@114 | 349 | // Write data to the bus. |
paul@114 | 350 | |
paul@114 | 351 | unsigned int |
paul@114 | 352 | I2c_jz4730_channel::write(uint8_t address, uint8_t buf[], unsigned int length) |
paul@114 | 353 | { |
paul@136 | 354 | _nwritten = 0; |
paul@136 | 355 | _length = length; |
paul@136 | 356 | _address = address; |
paul@136 | 357 | _buf = &buf[0]; |
paul@136 | 358 | _read = false; |
paul@114 | 359 | |
paul@136 | 360 | communicate(); |
paul@114 | 361 | |
paul@136 | 362 | return _nwritten; |
paul@114 | 363 | } |
paul@114 | 364 | |
paul@114 | 365 | // Test for data validity. |
paul@114 | 366 | |
paul@114 | 367 | bool |
paul@114 | 368 | I2c_jz4730_channel::data_valid() |
paul@114 | 369 | { |
paul@114 | 370 | return (_regs[I2c_status] & I2c_status_data_valid) ? true : false; |
paul@114 | 371 | } |
paul@114 | 372 | |
paul@114 | 373 | // Request the next byte by clearing the data validity flag. |
paul@114 | 374 | |
paul@114 | 375 | void |
paul@118 | 376 | I2c_jz4730_channel::clear_next() |
paul@114 | 377 | { |
paul@114 | 378 | _regs[I2c_status] = _regs[I2c_status] & ~I2c_status_data_valid; |
paul@114 | 379 | } |
paul@114 | 380 | |
paul@114 | 381 | // Indicate data ready for sending. |
paul@114 | 382 | |
paul@114 | 383 | void |
paul@114 | 384 | I2c_jz4730_channel::send_next() |
paul@114 | 385 | { |
paul@114 | 386 | _regs[I2c_status] = _regs[I2c_status] | I2c_status_data_valid; |
paul@114 | 387 | } |
paul@114 | 388 | |
paul@114 | 389 | // Test for non-acknowledgement. |
paul@114 | 390 | |
paul@114 | 391 | bool |
paul@114 | 392 | I2c_jz4730_channel::nack() |
paul@114 | 393 | { |
paul@114 | 394 | return (_regs[I2c_status] & I2c_status_nack) ? true : false; |
paul@114 | 395 | } |
paul@114 | 396 | |
paul@114 | 397 | // Set non-acknowledgement when receiving data. |
paul@114 | 398 | |
paul@114 | 399 | void |
paul@114 | 400 | I2c_jz4730_channel::signal_last() |
paul@114 | 401 | { |
paul@114 | 402 | _regs[I2c_control] = _regs[I2c_control] | I2c_control_nack; |
paul@114 | 403 | } |
paul@114 | 404 | |
paul@118 | 405 | // Test for bus activity. |
paul@118 | 406 | |
paul@118 | 407 | bool |
paul@118 | 408 | I2c_jz4730_channel::busy() |
paul@118 | 409 | { |
paul@118 | 410 | return (_regs[I2c_status] & I2c_status_busy) ? true : false; |
paul@118 | 411 | } |
paul@118 | 412 | |
paul@118 | 413 | // Test for transfer activity. |
paul@118 | 414 | |
paul@118 | 415 | bool |
paul@118 | 416 | I2c_jz4730_channel::transferring() |
paul@118 | 417 | { |
paul@118 | 418 | return (_regs[I2c_status] & I2c_status_buffer_nempty) ? true : false; |
paul@118 | 419 | } |
paul@118 | 420 | |
paul@114 | 421 | // Test for write transfer completion. |
paul@114 | 422 | |
paul@114 | 423 | bool |
paul@114 | 424 | I2c_jz4730_channel::transferred() |
paul@114 | 425 | { |
paul@114 | 426 | return (_regs[I2c_status] & I2c_status_transmit_end) ? true : false; |
paul@114 | 427 | } |
paul@114 | 428 | |
paul@114 | 429 | // Explicitly start communication. |
paul@114 | 430 | |
paul@114 | 431 | void |
paul@114 | 432 | I2c_jz4730_channel::start() |
paul@114 | 433 | { |
paul@114 | 434 | _regs[I2c_control] = (_regs[I2c_control] & ~I2c_control_nack) | I2c_control_start; |
paul@114 | 435 | } |
paul@114 | 436 | |
paul@114 | 437 | // Explicitly stop communication. |
paul@114 | 438 | |
paul@114 | 439 | void |
paul@114 | 440 | I2c_jz4730_channel::stop() |
paul@114 | 441 | { |
paul@114 | 442 | _regs[I2c_control] = _regs[I2c_control] | I2c_control_stop; |
paul@114 | 443 | } |
paul@114 | 444 | |
paul@114 | 445 | |
paul@114 | 446 | |
paul@114 | 447 | // Initialise the I2C controller. |
paul@114 | 448 | |
paul@114 | 449 | I2c_jz4730_chip::I2c_jz4730_chip(l4_addr_t start, l4_addr_t end, |
paul@114 | 450 | Cpm_jz4730_chip *cpm, |
paul@114 | 451 | uint32_t frequency) |
paul@114 | 452 | : _start(start), _end(end), _cpm(cpm), _frequency(frequency) |
paul@114 | 453 | { |
paul@114 | 454 | } |
paul@114 | 455 | |
paul@114 | 456 | // Obtain a channel object. Only one channel is supported. |
paul@114 | 457 | |
paul@114 | 458 | I2c_jz4730_channel * |
paul@118 | 459 | I2c_jz4730_chip::get_channel(uint8_t channel, l4_cap_idx_t irq) |
paul@114 | 460 | { |
paul@114 | 461 | if (channel == 0) |
paul@118 | 462 | return new I2c_jz4730_channel(_start, _cpm, _frequency, irq); |
paul@114 | 463 | else |
paul@114 | 464 | throw -L4_EINVAL; |
paul@114 | 465 | } |
paul@114 | 466 | |
paul@114 | 467 | |
paul@114 | 468 | |
paul@114 | 469 | // C language interface functions. |
paul@114 | 470 | |
paul@114 | 471 | void *jz4730_i2c_init(l4_addr_t start, l4_addr_t end, void *cpm, uint32_t frequency) |
paul@114 | 472 | { |
paul@114 | 473 | return (void *) new I2c_jz4730_chip(start, end, static_cast<Cpm_jz4730_chip *>(cpm), frequency); |
paul@114 | 474 | } |
paul@114 | 475 | |
paul@118 | 476 | void *jz4730_i2c_get_channel(void *i2c, uint8_t channel, l4_cap_idx_t irq) |
paul@114 | 477 | { |
paul@118 | 478 | return static_cast<I2c_jz4730_chip *>(i2c)->get_channel(channel, irq); |
paul@114 | 479 | } |
paul@114 | 480 | |
paul@114 | 481 | void jz4730_i2c_disable(void *i2c_channel) |
paul@114 | 482 | { |
paul@114 | 483 | static_cast<I2c_jz4730_channel *>(i2c_channel)->disable(); |
paul@114 | 484 | } |
paul@114 | 485 | |
paul@114 | 486 | void jz4730_i2c_enable(void *i2c_channel) |
paul@114 | 487 | { |
paul@114 | 488 | static_cast<I2c_jz4730_channel *>(i2c_channel)->enable(); |
paul@114 | 489 | } |
paul@114 | 490 | |
paul@114 | 491 | unsigned int jz4730_i2c_read(void *i2c_channel, uint8_t address, uint8_t buf[], unsigned int length) |
paul@114 | 492 | { |
paul@114 | 493 | return static_cast<I2c_jz4730_channel *>(i2c_channel)->read(address, buf, length); |
paul@114 | 494 | } |
paul@114 | 495 | |
paul@114 | 496 | unsigned int jz4730_i2c_write(void *i2c_channel, uint8_t address, uint8_t buf[], unsigned int length) |
paul@114 | 497 | { |
paul@114 | 498 | return static_cast<I2c_jz4730_channel *>(i2c_channel)->write(address, buf, length); |
paul@114 | 499 | } |