paul@114 | 1 | /* |
paul@114 | 2 | * I2C support for the JZ4730. |
paul@114 | 3 | * |
paul@131 | 4 | * Copyright (C) 2017, 2018, 2020, 2021 Paul Boddie <paul@boddie.org.uk> |
paul@114 | 5 | * |
paul@114 | 6 | * This program is free software; you can redistribute it and/or |
paul@114 | 7 | * modify it under the terms of the GNU General Public License as |
paul@114 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@114 | 9 | * the License, or (at your option) any later version. |
paul@114 | 10 | * |
paul@114 | 11 | * This program is distributed in the hope that it will be useful, |
paul@114 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@114 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@114 | 14 | * GNU General Public License for more details. |
paul@114 | 15 | * |
paul@114 | 16 | * You should have received a copy of the GNU General Public License |
paul@114 | 17 | * along with this program; if not, write to the Free Software |
paul@114 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@114 | 19 | * Boston, MA 02110-1301, USA |
paul@114 | 20 | */ |
paul@114 | 21 | |
paul@114 | 22 | #include <l4/devices/i2c-jz4730.h> |
paul@114 | 23 | #include <l4/devices/hw_mmio_register_block.h> |
paul@114 | 24 | |
paul@114 | 25 | #include <l4/sys/icu.h> |
paul@118 | 26 | #include <l4/sys/ipc.h> |
paul@118 | 27 | #include <l4/sys/irq.h> |
paul@114 | 28 | #include <l4/util/util.h> |
paul@114 | 29 | |
paul@114 | 30 | #include <cstdio> |
paul@114 | 31 | |
paul@114 | 32 | /* |
paul@114 | 33 | I2C pins are dedicated to I2C only and are not GPIO-controlled: |
paul@114 | 34 | |
paul@114 | 35 | I2C0: Y4/SMB0_SDA, V5/SMB0_SCK |
paul@114 | 36 | |
paul@114 | 37 | Note that there is effectively only one I2C channel. |
paul@114 | 38 | */ |
paul@114 | 39 | |
paul@114 | 40 | enum Regs |
paul@114 | 41 | { |
paul@114 | 42 | I2c_data = 0x000, // I2CDR |
paul@114 | 43 | I2c_control = 0x004, // I2CCR |
paul@114 | 44 | I2c_status = 0x008, // I2CSR |
paul@114 | 45 | I2c_clock = 0x00c, // I2CGR |
paul@114 | 46 | }; |
paul@114 | 47 | |
paul@114 | 48 | enum I2c_control_bits : unsigned |
paul@114 | 49 | { |
paul@114 | 50 | I2c_control_enable_irq = 0x10, // IEN |
paul@114 | 51 | I2c_control_start = 0x08, // STA |
paul@114 | 52 | I2c_control_stop = 0x04, // STO |
paul@114 | 53 | I2c_control_nack = 0x02, // AC |
paul@114 | 54 | I2c_control_enable = 0x01, // I2CE |
paul@114 | 55 | }; |
paul@114 | 56 | |
paul@114 | 57 | enum I2c_status_bits : unsigned |
paul@114 | 58 | { |
paul@114 | 59 | I2c_status_buffer_nempty = 0x10, // STX |
paul@114 | 60 | I2c_status_busy = 0x08, // BUSY |
paul@114 | 61 | I2c_status_transmit_end = 0x04, // TEND |
paul@114 | 62 | I2c_status_data_valid = 0x02, // DRF |
paul@114 | 63 | I2c_status_nack = 0x01, // ACKF |
paul@114 | 64 | }; |
paul@114 | 65 | |
paul@114 | 66 | enum I2c_clock_values : unsigned |
paul@114 | 67 | { |
paul@114 | 68 | I2c_clock_max = 0xffff, |
paul@114 | 69 | I2c_clock_min = 0, |
paul@114 | 70 | }; |
paul@114 | 71 | |
paul@114 | 72 | |
paul@114 | 73 | |
paul@114 | 74 | // Initialise a channel. |
paul@114 | 75 | |
paul@114 | 76 | I2c_jz4730_channel::I2c_jz4730_channel(l4_addr_t start, |
paul@114 | 77 | Cpm_jz4730_chip *cpm, |
paul@118 | 78 | uint32_t frequency, |
paul@118 | 79 | l4_cap_idx_t irq) |
paul@118 | 80 | : _cpm(cpm), _frequency(frequency), _irq(irq) |
paul@114 | 81 | { |
paul@114 | 82 | _regs = new Hw::Mmio_register_block<32>(start); |
paul@114 | 83 | } |
paul@114 | 84 | |
paul@114 | 85 | // Enable the channel. |
paul@114 | 86 | |
paul@114 | 87 | void |
paul@114 | 88 | I2c_jz4730_channel::enable() |
paul@114 | 89 | { |
paul@114 | 90 | // Make sure that the I2C clock is available. |
paul@114 | 91 | |
paul@128 | 92 | _cpm->start_clock(Clock_i2c); |
paul@114 | 93 | |
paul@114 | 94 | // Set the bus clock frequency. |
paul@114 | 95 | |
paul@114 | 96 | set_frequency(); |
paul@114 | 97 | |
paul@114 | 98 | // Enable the channel and interrupts. |
paul@114 | 99 | |
paul@114 | 100 | _regs[I2c_control] = I2c_control_enable | I2c_control_enable_irq; |
paul@114 | 101 | while (!(_regs[I2c_control] & I2c_control_enable)); |
paul@114 | 102 | } |
paul@114 | 103 | |
paul@114 | 104 | // Disable the channel. |
paul@114 | 105 | |
paul@114 | 106 | void |
paul@114 | 107 | I2c_jz4730_channel::disable() |
paul@114 | 108 | { |
paul@114 | 109 | _regs[I2c_control] = 0; |
paul@114 | 110 | while (_regs[I2c_control] & I2c_control_enable); |
paul@114 | 111 | } |
paul@114 | 112 | |
paul@114 | 113 | // Set the frequency-related peripheral parameters. |
paul@114 | 114 | |
paul@114 | 115 | void |
paul@114 | 116 | I2c_jz4730_channel::set_frequency() |
paul@114 | 117 | { |
paul@114 | 118 | // The APB clock (PCLK) is used to drive I2C transfers. Its value must be |
paul@114 | 119 | // obtained from the CPM unit and is scaled to kHz in order to keep the |
paul@114 | 120 | // numbers easily representable, as is the bus frequency. |
paul@114 | 121 | |
paul@114 | 122 | uint32_t pclk = _cpm->get_pclock_frequency() / 1000; |
paul@114 | 123 | uint32_t i2c_clk = _frequency / 1000; |
paul@114 | 124 | uint32_t division = pclk / (16 * i2c_clk); |
paul@114 | 125 | |
paul@114 | 126 | if (division > I2c_clock_min) |
paul@114 | 127 | { |
paul@114 | 128 | division -= 1; |
paul@114 | 129 | if (division > I2c_clock_max) |
paul@114 | 130 | division = I2c_clock_max; |
paul@114 | 131 | } |
paul@114 | 132 | |
paul@114 | 133 | _regs[I2c_clock] = division; |
paul@114 | 134 | } |
paul@114 | 135 | |
paul@114 | 136 | // Present the address on the bus. |
paul@114 | 137 | |
paul@118 | 138 | bool |
paul@114 | 139 | I2c_jz4730_channel::set_address(uint8_t address, bool read) |
paul@114 | 140 | { |
paul@124 | 141 | // Waiting for long enough may eliminate a busy condition and thus permit a |
paul@124 | 142 | // new transaction. 10ms appears to be long enough, whereas 1ms does not |
paul@124 | 143 | // appear to be. In case this is insufficient, permit failure. |
paul@124 | 144 | |
paul@118 | 145 | unsigned int limit = 10; |
paul@118 | 146 | |
paul@118 | 147 | do |
paul@118 | 148 | { |
paul@118 | 149 | if (!wait_for_irq(1000) && !(--limit)) |
paul@118 | 150 | return false; |
paul@118 | 151 | } |
paul@118 | 152 | while (busy()); |
paul@118 | 153 | |
paul@114 | 154 | start(); |
paul@114 | 155 | |
paul@116 | 156 | _regs[I2c_data] = (address << 1) | (read ? 1 : 0); |
paul@114 | 157 | |
paul@114 | 158 | send_next(); |
paul@114 | 159 | |
paul@118 | 160 | return true; |
paul@118 | 161 | } |
paul@118 | 162 | |
paul@118 | 163 | // Wait up to the given timeout (in microseconds) for an interrupt request, |
paul@118 | 164 | // returning true if one was delivered. |
paul@118 | 165 | |
paul@118 | 166 | bool |
paul@118 | 167 | I2c_jz4730_channel::wait_for_irq(unsigned int timeout) |
paul@118 | 168 | { |
paul@118 | 169 | return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, l4util_micros2l4to(timeout)))); |
paul@114 | 170 | } |
paul@114 | 171 | |
paul@114 | 172 | // Read data from the bus. |
paul@114 | 173 | |
paul@114 | 174 | unsigned int |
paul@114 | 175 | I2c_jz4730_channel::read(uint8_t address, uint8_t buf[], unsigned int length) |
paul@114 | 176 | { |
paul@114 | 177 | unsigned int nread = 0; |
paul@114 | 178 | |
paul@118 | 179 | if (!set_address(address, true)) |
paul@118 | 180 | return 0; |
paul@118 | 181 | |
paul@131 | 182 | // Wait for an opportunity to begin reading. |
paul@131 | 183 | |
paul@118 | 184 | do |
paul@118 | 185 | { |
paul@118 | 186 | if (!wait_for_irq(1000000)) |
paul@118 | 187 | printf("start (no irq): status = %x\n", (uint32_t) _regs[I2c_status]); |
paul@118 | 188 | } |
paul@118 | 189 | while (transferring() || (!data_valid() && !nack())); |
paul@114 | 190 | |
paul@131 | 191 | // Device apparently unavailable. |
paul@131 | 192 | |
paul@131 | 193 | if (nack()) |
paul@131 | 194 | { |
paul@131 | 195 | stop(); |
paul@131 | 196 | return nread; |
paul@131 | 197 | } |
paul@131 | 198 | |
paul@131 | 199 | // Attempt to read from the device. |
paul@131 | 200 | |
paul@118 | 201 | while (nread < length) |
paul@114 | 202 | { |
paul@118 | 203 | do |
paul@118 | 204 | { |
paul@118 | 205 | if (!wait_for_irq(1000000)) |
paul@118 | 206 | { |
paul@118 | 207 | stop(); |
paul@118 | 208 | return nread; |
paul@118 | 209 | } |
paul@118 | 210 | } |
paul@118 | 211 | while (!data_valid() && !nack()); |
paul@118 | 212 | |
paul@118 | 213 | if (nack()) |
paul@118 | 214 | break; |
paul@118 | 215 | |
paul@118 | 216 | if ((!nread && (length == 1)) || (nread == length - 2)) |
paul@114 | 217 | signal_last(); |
paul@114 | 218 | |
paul@118 | 219 | buf[nread++] = _regs[I2c_data]; |
paul@118 | 220 | clear_next(); |
paul@114 | 221 | } |
paul@114 | 222 | |
paul@114 | 223 | stop(); |
paul@114 | 224 | return nread; |
paul@114 | 225 | } |
paul@114 | 226 | |
paul@114 | 227 | // Write data to the bus. |
paul@114 | 228 | |
paul@114 | 229 | unsigned int |
paul@114 | 230 | I2c_jz4730_channel::write(uint8_t address, uint8_t buf[], unsigned int length) |
paul@114 | 231 | { |
paul@114 | 232 | unsigned int nwritten = 0; |
paul@114 | 233 | |
paul@118 | 234 | if (!set_address(address, false)) |
paul@118 | 235 | return 0; |
paul@118 | 236 | |
paul@118 | 237 | do |
paul@118 | 238 | { |
paul@118 | 239 | if (!wait_for_irq(1000000)) |
paul@118 | 240 | { |
paul@118 | 241 | printf("write (no irq): status = %x\n", (uint32_t) _regs[I2c_status]); |
paul@118 | 242 | stop(); |
paul@118 | 243 | return nwritten; |
paul@118 | 244 | } |
paul@118 | 245 | } |
paul@118 | 246 | while (data_valid() && !nack()); |
paul@114 | 247 | |
paul@114 | 248 | while ((nwritten < length) && !nack()) |
paul@114 | 249 | { |
paul@114 | 250 | _regs[I2c_data] = buf[nwritten++]; |
paul@114 | 251 | send_next(); |
paul@114 | 252 | |
paul@118 | 253 | do |
paul@118 | 254 | { |
paul@118 | 255 | if (!wait_for_irq(1000000)) |
paul@118 | 256 | { |
paul@118 | 257 | printf("write (no irq): status = %x\n", (uint32_t) _regs[I2c_status]); |
paul@118 | 258 | stop(); |
paul@118 | 259 | return nwritten; |
paul@118 | 260 | } |
paul@118 | 261 | } |
paul@114 | 262 | while (data_valid() && !nack()); |
paul@114 | 263 | } |
paul@114 | 264 | |
paul@114 | 265 | stop(); |
paul@114 | 266 | |
paul@118 | 267 | do |
paul@118 | 268 | { |
paul@118 | 269 | if (!wait_for_irq(1000000)) |
paul@118 | 270 | break; |
paul@118 | 271 | } |
paul@114 | 272 | while (!transferred()); |
paul@114 | 273 | |
paul@114 | 274 | return nwritten; |
paul@114 | 275 | } |
paul@114 | 276 | |
paul@114 | 277 | // Test for data validity. |
paul@114 | 278 | |
paul@114 | 279 | bool |
paul@114 | 280 | I2c_jz4730_channel::data_valid() |
paul@114 | 281 | { |
paul@114 | 282 | return (_regs[I2c_status] & I2c_status_data_valid) ? true : false; |
paul@114 | 283 | } |
paul@114 | 284 | |
paul@114 | 285 | // Request the next byte by clearing the data validity flag. |
paul@114 | 286 | |
paul@114 | 287 | void |
paul@118 | 288 | I2c_jz4730_channel::clear_next() |
paul@114 | 289 | { |
paul@114 | 290 | _regs[I2c_status] = _regs[I2c_status] & ~I2c_status_data_valid; |
paul@114 | 291 | } |
paul@114 | 292 | |
paul@114 | 293 | // Indicate data ready for sending. |
paul@114 | 294 | |
paul@114 | 295 | void |
paul@114 | 296 | I2c_jz4730_channel::send_next() |
paul@114 | 297 | { |
paul@114 | 298 | _regs[I2c_status] = _regs[I2c_status] | I2c_status_data_valid; |
paul@114 | 299 | } |
paul@114 | 300 | |
paul@114 | 301 | // Test for non-acknowledgement. |
paul@114 | 302 | |
paul@114 | 303 | bool |
paul@114 | 304 | I2c_jz4730_channel::nack() |
paul@114 | 305 | { |
paul@114 | 306 | return (_regs[I2c_status] & I2c_status_nack) ? true : false; |
paul@114 | 307 | } |
paul@114 | 308 | |
paul@114 | 309 | // Set non-acknowledgement when receiving data. |
paul@114 | 310 | |
paul@114 | 311 | void |
paul@114 | 312 | I2c_jz4730_channel::signal_last() |
paul@114 | 313 | { |
paul@114 | 314 | _regs[I2c_control] = _regs[I2c_control] | I2c_control_nack; |
paul@114 | 315 | } |
paul@114 | 316 | |
paul@118 | 317 | // Test for bus activity. |
paul@118 | 318 | |
paul@118 | 319 | bool |
paul@118 | 320 | I2c_jz4730_channel::busy() |
paul@118 | 321 | { |
paul@118 | 322 | return (_regs[I2c_status] & I2c_status_busy) ? true : false; |
paul@118 | 323 | } |
paul@118 | 324 | |
paul@118 | 325 | // Test for transfer activity. |
paul@118 | 326 | |
paul@118 | 327 | bool |
paul@118 | 328 | I2c_jz4730_channel::transferring() |
paul@118 | 329 | { |
paul@118 | 330 | return (_regs[I2c_status] & I2c_status_buffer_nempty) ? true : false; |
paul@118 | 331 | } |
paul@118 | 332 | |
paul@114 | 333 | // Test for write transfer completion. |
paul@114 | 334 | |
paul@114 | 335 | bool |
paul@114 | 336 | I2c_jz4730_channel::transferred() |
paul@114 | 337 | { |
paul@114 | 338 | return (_regs[I2c_status] & I2c_status_transmit_end) ? true : false; |
paul@114 | 339 | } |
paul@114 | 340 | |
paul@114 | 341 | // Explicitly start communication. |
paul@114 | 342 | |
paul@114 | 343 | void |
paul@114 | 344 | I2c_jz4730_channel::start() |
paul@114 | 345 | { |
paul@114 | 346 | _regs[I2c_control] = (_regs[I2c_control] & ~I2c_control_nack) | I2c_control_start; |
paul@114 | 347 | } |
paul@114 | 348 | |
paul@114 | 349 | // Explicitly stop communication. |
paul@114 | 350 | |
paul@114 | 351 | void |
paul@114 | 352 | I2c_jz4730_channel::stop() |
paul@114 | 353 | { |
paul@114 | 354 | _regs[I2c_control] = _regs[I2c_control] | I2c_control_stop; |
paul@114 | 355 | } |
paul@114 | 356 | |
paul@114 | 357 | |
paul@114 | 358 | |
paul@114 | 359 | // Initialise the I2C controller. |
paul@114 | 360 | |
paul@114 | 361 | I2c_jz4730_chip::I2c_jz4730_chip(l4_addr_t start, l4_addr_t end, |
paul@114 | 362 | Cpm_jz4730_chip *cpm, |
paul@114 | 363 | uint32_t frequency) |
paul@114 | 364 | : _start(start), _end(end), _cpm(cpm), _frequency(frequency) |
paul@114 | 365 | { |
paul@114 | 366 | } |
paul@114 | 367 | |
paul@114 | 368 | // Obtain a channel object. Only one channel is supported. |
paul@114 | 369 | |
paul@114 | 370 | I2c_jz4730_channel * |
paul@118 | 371 | I2c_jz4730_chip::get_channel(uint8_t channel, l4_cap_idx_t irq) |
paul@114 | 372 | { |
paul@114 | 373 | if (channel == 0) |
paul@118 | 374 | return new I2c_jz4730_channel(_start, _cpm, _frequency, irq); |
paul@114 | 375 | else |
paul@114 | 376 | throw -L4_EINVAL; |
paul@114 | 377 | } |
paul@114 | 378 | |
paul@114 | 379 | |
paul@114 | 380 | |
paul@114 | 381 | // C language interface functions. |
paul@114 | 382 | |
paul@114 | 383 | void *jz4730_i2c_init(l4_addr_t start, l4_addr_t end, void *cpm, uint32_t frequency) |
paul@114 | 384 | { |
paul@114 | 385 | return (void *) new I2c_jz4730_chip(start, end, static_cast<Cpm_jz4730_chip *>(cpm), frequency); |
paul@114 | 386 | } |
paul@114 | 387 | |
paul@118 | 388 | void *jz4730_i2c_get_channel(void *i2c, uint8_t channel, l4_cap_idx_t irq) |
paul@114 | 389 | { |
paul@118 | 390 | return static_cast<I2c_jz4730_chip *>(i2c)->get_channel(channel, irq); |
paul@114 | 391 | } |
paul@114 | 392 | |
paul@114 | 393 | void jz4730_i2c_disable(void *i2c_channel) |
paul@114 | 394 | { |
paul@114 | 395 | static_cast<I2c_jz4730_channel *>(i2c_channel)->disable(); |
paul@114 | 396 | } |
paul@114 | 397 | |
paul@114 | 398 | void jz4730_i2c_enable(void *i2c_channel) |
paul@114 | 399 | { |
paul@114 | 400 | static_cast<I2c_jz4730_channel *>(i2c_channel)->enable(); |
paul@114 | 401 | } |
paul@114 | 402 | |
paul@114 | 403 | unsigned int jz4730_i2c_read(void *i2c_channel, uint8_t address, uint8_t buf[], unsigned int length) |
paul@114 | 404 | { |
paul@114 | 405 | return static_cast<I2c_jz4730_channel *>(i2c_channel)->read(address, buf, length); |
paul@114 | 406 | } |
paul@114 | 407 | |
paul@114 | 408 | unsigned int jz4730_i2c_write(void *i2c_channel, uint8_t address, uint8_t buf[], unsigned int length) |
paul@114 | 409 | { |
paul@114 | 410 | return static_cast<I2c_jz4730_channel *>(i2c_channel)->write(address, buf, length); |
paul@114 | 411 | } |