paul@62 | 1 | /* |
paul@62 | 2 | * JZ4780 HDMI peripheral support. |
paul@62 | 3 | * |
paul@62 | 4 | * Copyright (C) 2020 Paul Boddie <paul@boddie.org.uk> |
paul@62 | 5 | * |
paul@66 | 6 | * Techniques and operations introduced from the Linux DRM bridge driver for |
paul@66 | 7 | * Synopsys DW-HDMI whose authors are as follows: |
paul@66 | 8 | * |
paul@66 | 9 | * Copyright (C) 2013-2015 Mentor Graphics Inc. |
paul@66 | 10 | * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. |
paul@66 | 11 | * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
paul@66 | 12 | * |
paul@62 | 13 | * This program is free software; you can redistribute it and/or |
paul@62 | 14 | * modify it under the terms of the GNU General Public License as |
paul@62 | 15 | * published by the Free Software Foundation; either version 2 of |
paul@62 | 16 | * the License, or (at your option) any later version. |
paul@62 | 17 | * |
paul@62 | 18 | * This program is distributed in the hope that it will be useful, |
paul@62 | 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@62 | 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@62 | 21 | * GNU General Public License for more details. |
paul@62 | 22 | * |
paul@62 | 23 | * You should have received a copy of the GNU General Public License |
paul@62 | 24 | * along with this program; if not, write to the Free Software |
paul@62 | 25 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@62 | 26 | * Boston, MA 02110-1301, USA |
paul@66 | 27 | * |
paul@66 | 28 | * ---- |
paul@66 | 29 | * |
paul@66 | 30 | * Some acronyms: |
paul@66 | 31 | * |
paul@66 | 32 | * CEC (Consumer Electronics Control) is a HDMI device control interface for up |
paul@66 | 33 | * to 15 devices. |
paul@66 | 34 | * |
paul@66 | 35 | * CSC (Colour Space Conversion) is the processing needed to convert from one |
paul@66 | 36 | * representation of colours to another. |
paul@66 | 37 | * |
paul@66 | 38 | * HEAC (HDMI Ethernet and Audio Return Channel) is a combination of HEC (HDMI |
paul@66 | 39 | * Ethernet Channel) which provides a 100Mb/s bidirectional link and ARC (Audio |
paul@66 | 40 | * Return Channel) which permits the consumption of audio data from the device. |
paul@66 | 41 | * |
paul@66 | 42 | * MHL (Mobile High-Definition Link) is an adaptation of HDMI for mobile |
paul@66 | 43 | * devices. |
paul@66 | 44 | * |
paul@66 | 45 | * TMDS (Transition-Minimized Differential Signaling) is the method by which |
paul@66 | 46 | * audio, control and video data are all sent to the device. |
paul@62 | 47 | */ |
paul@62 | 48 | |
paul@62 | 49 | #include <l4/devices/hdmi-jz4780.h> |
paul@62 | 50 | #include <l4/devices/hw_mmio_register_block.h> |
paul@66 | 51 | #include <l4/devices/lcd-jz4740-config.h> |
paul@62 | 52 | |
paul@62 | 53 | #include <l4/sys/irq.h> |
paul@62 | 54 | #include <l4/util/util.h> |
paul@62 | 55 | |
paul@62 | 56 | /* |
paul@62 | 57 | I2C pins: |
paul@62 | 58 | |
paul@62 | 59 | HDMI: PF25/SMB4_SDA/DDCSDA, PF24/SMB4_SCK/DDCSCK |
paul@62 | 60 | |
paul@62 | 61 | See: http://mipscreator.imgtec.com/CI20/hardware/board/ci20_jz4780_v2.0.pdf |
paul@62 | 62 | */ |
paul@62 | 63 | |
paul@62 | 64 | enum Regs |
paul@62 | 65 | { |
paul@62 | 66 | // Identification. |
paul@62 | 67 | |
paul@66 | 68 | Design_id = 0x000, // DESIGN_ID |
paul@66 | 69 | Revision_id = 0x001, // REVISION_ID |
paul@66 | 70 | Product_id0 = 0x002, // PRODUCT_ID0 |
paul@66 | 71 | Product_id1 = 0x003, // PRODUCT_ID1 |
paul@66 | 72 | Config_id0 = 0x004, // CONFIG_ID0 |
paul@66 | 73 | Config_id1 = 0x005, // CONFIG_ID1 |
paul@66 | 74 | Config_id2 = 0x006, // CONFIG_ID2 |
paul@66 | 75 | Config_id3 = 0x007, // CONFIG_ID3 |
paul@62 | 76 | |
paul@62 | 77 | // Top-level interrupt control. |
paul@62 | 78 | |
paul@66 | 79 | Int_mask = 0x1ff, // MUTE |
paul@62 | 80 | |
paul@62 | 81 | // Interrupt status and mask for various functions. |
paul@62 | 82 | |
paul@66 | 83 | Fc_int_status0 = 0x100, // FC_STAT0 |
paul@66 | 84 | Fc_int_status1 = 0x101, // FC_STAT1 |
paul@66 | 85 | Fc_int_status2 = 0x102, // FC_STAT2 |
paul@66 | 86 | As_int_status = 0x103, // AS_STAT0 |
paul@66 | 87 | Phy_int_status = 0x104, // PHY_STAT0 |
paul@66 | 88 | Cec_int_status = 0x106, // CEC_STAT0 |
paul@66 | 89 | Vp_int_status = 0x107, // VP_STAT0 |
paul@66 | 90 | Ahb_dma_audio_int_status = 0x109, // AHBDMAAUD_STAT0 |
paul@62 | 91 | |
paul@66 | 92 | Fc_int_mask0 = 0x180, // MUTE_FC_STAT0 |
paul@66 | 93 | Fc_int_mask1 = 0x181, // MUTE_FC_STAT1 |
paul@66 | 94 | Fc_int_mask2 = 0x182, // MUTE_FC_STAT2 |
paul@66 | 95 | As_int_mask = 0x183, // MUTE_AS_STAT0 |
paul@66 | 96 | Phy_int_mask = 0x184, // MUTE_PHY_STAT0 |
paul@66 | 97 | Cec_int_mask = 0x186, // MUTE_CEC_STAT0 |
paul@66 | 98 | Vp_int_mask = 0x187, // MUTE_VP_STAT0 |
paul@66 | 99 | Ahb_dma_audio_int_mask = 0x189, // MUTE_AHBDMAAUD_STAT0 |
paul@62 | 100 | |
paul@62 | 101 | // I2C for E-DDC. |
paul@62 | 102 | |
paul@66 | 103 | I2c_int_status = 0x105, // I2CM_STAT0 |
paul@66 | 104 | I2c_int_mask = 0x185, // MUTE_I2CM_STAT0 |
paul@62 | 105 | |
paul@66 | 106 | I2c_device_address = 0x7e00, // I2CM_SLAVE |
paul@66 | 107 | I2c_register = 0x7e01, // I2CM_ADDRESS |
paul@66 | 108 | I2c_data_out = 0x7e02, // I2CM_DATAO |
paul@66 | 109 | I2c_data_in = 0x7e03, // I2CM_DATAI |
paul@66 | 110 | I2c_operation = 0x7e04, // I2CM_OPERATION |
paul@66 | 111 | I2c_int_config0 = 0x7e05, // I2CM_INT |
paul@66 | 112 | I2c_int_config1 = 0x7e06, // I2CM_CTLINT |
paul@66 | 113 | I2c_divider = 0x7e07, // I2CM_DIV |
paul@66 | 114 | I2c_segment_address = 0x7e08, // I2CM_SEGADDR |
paul@66 | 115 | I2c_software_reset = 0x7e09, // I2CM_SOFTRSTZ |
paul@66 | 116 | I2c_segment_pointer = 0x7e0a, // I2CM_SEGPTR |
paul@62 | 117 | |
paul@62 | 118 | // I2C for PHY. |
paul@62 | 119 | |
paul@66 | 120 | I2c_phy_int_status = 0x108, // I2CMPHY_STAT0 |
paul@66 | 121 | I2c_phy_int_mask = 0x188, // MUTE_I2CMPHY_STAT0 |
paul@62 | 122 | |
paul@66 | 123 | I2c_phy_device_address = 0x3020, // PHY_I2CM_SLAVE_ADDR |
paul@66 | 124 | I2c_phy_register = 0x3021, // PHY_I2CM_ADDRESS_ADDR |
paul@66 | 125 | I2c_phy_data_out1 = 0x3022, // PHY_I2CM_DATAO_1_ADDR |
paul@66 | 126 | I2c_phy_data_out0 = 0x3023, // PHY_I2CM_DATAO_0_ADDR |
paul@66 | 127 | I2c_phy_data_in1 = 0x3024, // PHY_I2CM_DATAI_1_ADDR |
paul@66 | 128 | I2c_phy_data_in0 = 0x3025, // PHY_I2CM_DATAI_0_ADDR |
paul@66 | 129 | I2c_phy_operation = 0x3026, // PHY_I2CM_OPERATION_ADDR |
paul@66 | 130 | I2c_phy_int_config0 = 0x3027, // PHY_I2CM_INT_ADDR |
paul@66 | 131 | I2c_phy_int_config1 = 0x3028, // PHY_I2CM_CTLINT_ADDR |
paul@66 | 132 | I2c_phy_divider = 0x3029, // PHY_I2CM_DIV_ADDR |
paul@66 | 133 | I2c_phy_software_reset = 0x302a, // PHY_I2CM_SOFTRSTZ_ADDR |
paul@65 | 134 | |
paul@65 | 135 | // PHY registers. |
paul@65 | 136 | |
paul@66 | 137 | Phy_config = 0x3000, // PHY_CONF0 |
paul@66 | 138 | Phy_test0 = 0x3001, // PHY_TST0 |
paul@66 | 139 | Phy_test1 = 0x3002, // PHY_TST1 |
paul@66 | 140 | Phy_test2 = 0x3003, // PHY_TST2 |
paul@66 | 141 | Phy_status = 0x3004, // PHY_STAT0 |
paul@66 | 142 | Phy_int_config = 0x3005, // PHY_INT0 |
paul@66 | 143 | Phy_mask = 0x3006, // PHY_MASK0 |
paul@66 | 144 | Phy_polarity = 0x3007, // PHY_POL0 |
paul@66 | 145 | |
paul@66 | 146 | // Main controller registers. |
paul@66 | 147 | |
paul@66 | 148 | Main_clock_disable = 0x4001, // MC_CLKDIS |
paul@66 | 149 | Main_software_reset = 0x4002, // MC_SWRSTZ |
paul@66 | 150 | Main_flow_control = 0x4004, // MC_FLOWCTRL |
paul@66 | 151 | Main_reset = 0x4005, // MC_PHYRSTZ |
paul@66 | 152 | Main_heac_phy_reset = 0x4007, // MC_HEACPHY_RST |
paul@66 | 153 | |
paul@66 | 154 | // Frame composer registers for input video. |
paul@66 | 155 | |
paul@66 | 156 | Fc_video_config = 0x1000, // FC_INVIDCONF |
paul@66 | 157 | Fc_horizontal_active_width0 = 0x1001, // FC_INHACTV0 |
paul@66 | 158 | Fc_horizontal_active_width1 = 0x1002, // FC_INHACTV1 |
paul@66 | 159 | Fc_horizontal_blank_width0 = 0x1003, // FC_INHBLANK0 |
paul@66 | 160 | Fc_horizontal_blank_width1 = 0x1004, // FC_INHBLANK1 |
paul@66 | 161 | Fc_vertical_active_height0 = 0x1005, // FC_INVACTV0 |
paul@66 | 162 | Fc_vertical_active_height1 = 0x1006, // FC_INVACTV1 |
paul@66 | 163 | Fc_vertical_blank_height = 0x1007, // FC_INVBLANK |
paul@66 | 164 | |
paul@66 | 165 | // Frame composer registers for sync pulses. |
paul@66 | 166 | |
paul@66 | 167 | Fc_hsync_delay0 = 0x1008, // FC_HSYNCINDELAY0 |
paul@66 | 168 | Fc_hsync_delay1 = 0x1009, // FC_HSYNCINDELAY1 |
paul@66 | 169 | Fc_hsync_width0 = 0x100A, // FC_HSYNCINWIDTH0 |
paul@66 | 170 | Fc_hsync_width1 = 0x100B, // FC_HSYNCINWIDTH1 |
paul@66 | 171 | Fc_vsync_delay = 0x100C, // FC_VSYNCINDELAY |
paul@66 | 172 | Fc_vsync_height = 0x100D, // FC_VSYNCINWIDTH |
paul@66 | 173 | |
paul@66 | 174 | // Frame composer registers for video path configuration. |
paul@66 | 175 | |
paul@66 | 176 | Fc_control_duration = 0x1011, // FC_CTRLDUR |
paul@66 | 177 | Fc_ex_control_duration = 0x1012, // FC_EXCTRLDUR |
paul@66 | 178 | Fc_ex_control_space = 0x1013, // FC_EXCTRLSPAC |
paul@66 | 179 | Fc_channel0_preamble = 0x1014, // FC_CH0PREAM |
paul@66 | 180 | Fc_channel1_preamble = 0x1015, // FC_CH1PREAM |
paul@66 | 181 | Fc_channel2_preamble = 0x1016, // FC_CH2PREAM |
paul@66 | 182 | |
paul@66 | 183 | // Colour space conversion registers. |
paul@66 | 184 | |
paul@66 | 185 | Csc_config = 0x4100, // CSC_CFG |
paul@66 | 186 | Csc_scale = 0x4101, // CSC_SCALE |
paul@66 | 187 | |
paul@66 | 188 | // HDCP registers. |
paul@66 | 189 | |
paul@66 | 190 | Hdcp_config0 = 0x5000, // A_HDCPCFG0 |
paul@66 | 191 | Hdcp_config1 = 0x5001, // A_HDCPCFG1 |
paul@66 | 192 | Hdcp_video_polarity = 0x5009, // A_VIDPOLCFG |
paul@66 | 193 | |
paul@66 | 194 | // Video sample registers. |
paul@66 | 195 | |
paul@66 | 196 | Sample_video_config = 0x0200, // TX_INVID0 |
paul@66 | 197 | Sample_video_stuffing = 0x0201, // TX_INSTUFFING |
paul@66 | 198 | Sample_gy_data0 = 0x0202, // TX_GYDATA0 |
paul@66 | 199 | Sample_gy_data1 = 0x0203, // TX_GYDATA1 |
paul@66 | 200 | Sample_rcr_data0 = 0x0204, // TX_RCRDATA0 |
paul@66 | 201 | Sample_rcr_data1 = 0x0205, // TX_RCRDATA1 |
paul@66 | 202 | Sample_bcb_data0 = 0x0206, // TX_BCBDATA0 |
paul@66 | 203 | Sample_bcb_data1 = 0x0207, // TX_BCBDATA1 |
paul@66 | 204 | |
paul@66 | 205 | // Video packetizer registers. |
paul@66 | 206 | |
paul@66 | 207 | Packet_status = 0x0800, // VP_STATUS |
paul@71 | 208 | Packet_pr_cd = 0x0801, // VP_PR_CD |
paul@66 | 209 | Packet_stuffing = 0x0802, // VP_STUFF |
paul@66 | 210 | Packet_remap = 0x0803, // VP_REMAP |
paul@66 | 211 | Packet_config = 0x0804, // VP_CONF |
paul@62 | 212 | }; |
paul@62 | 213 | |
paul@62 | 214 | // Identification values. |
paul@62 | 215 | |
paul@71 | 216 | enum Product_id_values : uint8_t |
paul@62 | 217 | { |
paul@65 | 218 | Product_id0_transmitter = 0xa0, // PRODUCT_ID0_HDMI_TX |
paul@62 | 219 | |
paul@65 | 220 | Product_id1_hdcp = 0xc0, // PRODUCT_ID1_HDCP |
paul@65 | 221 | Product_id1_receiver = 0x02, // PRODUCT_ID1_HDMI_RX |
paul@65 | 222 | Product_id1_transmitter = 0x01, // PRODUCT_ID1_HDMI_TX |
paul@62 | 223 | }; |
paul@62 | 224 | |
paul@62 | 225 | // Configuration values. |
paul@62 | 226 | |
paul@71 | 227 | enum Config_id_values : uint8_t |
paul@62 | 228 | { |
paul@62 | 229 | Config_id0_i2s = 0x10, // CONFIG0_I2S |
paul@62 | 230 | Config_id0_cec = 0x02, // CONFIG0_CEC |
paul@62 | 231 | |
paul@62 | 232 | Config_id1_ahb = 0x01, // CONFIG1_AHB |
paul@62 | 233 | |
paul@62 | 234 | Config2_dwc_hdmi_tx_phy = 0x00, // DWC_HDMI_TX_PHY |
paul@62 | 235 | Config2_dwc_mhl_phy_heac = 0xb2, // DWC_MHL_PHY_HEAC |
paul@62 | 236 | Config2_dwc_mhl_phy = 0xc2, // DWC_MHL_PHY |
paul@62 | 237 | Config2_dwc_hdmi_3d_tx_phy_heac = 0xe2, // DWC_HDMI_3D_TX_PHY_HEAC |
paul@62 | 238 | Config2_dwc_hdmi_3d_tx_phy = 0xf2, // DWC_HDMI_3D_TX_PHY |
paul@62 | 239 | Config2_dwc_hdmi20_tx_phy = 0xf3, // DWC_HDMI20_TX_PHY |
paul@62 | 240 | Config2_vendor_phy = 0xfe, // VENDOR_PHY |
paul@62 | 241 | |
paul@62 | 242 | Config_id3_ahb_audio_dma = 0x02, // CONFIG3_AHBAUDDMA |
paul@62 | 243 | Config_id3_gp_audio = 0x01, // CONFIG3_GPAUD |
paul@62 | 244 | }; |
paul@62 | 245 | |
paul@62 | 246 | // Status and mask bits. |
paul@62 | 247 | |
paul@71 | 248 | enum Int_mask_bits : uint8_t |
paul@62 | 249 | { |
paul@65 | 250 | Int_mask_wakeup = 0x02, |
paul@65 | 251 | Int_mask_all = 0x01, |
paul@62 | 252 | }; |
paul@62 | 253 | |
paul@66 | 254 | // I2C status and mask bits, also for PHY I2C. |
paul@66 | 255 | |
paul@71 | 256 | enum I2c_int_status_bits : uint8_t |
paul@62 | 257 | { |
paul@65 | 258 | I2c_int_status_done = 0x02, |
paul@65 | 259 | I2c_int_status_error = 0x01, |
paul@62 | 260 | }; |
paul@62 | 261 | |
paul@62 | 262 | // I2C operation bits. |
paul@62 | 263 | |
paul@71 | 264 | enum I2c_operation_bits : uint8_t |
paul@62 | 265 | { |
paul@65 | 266 | I2c_operation_write = 0x10, |
paul@66 | 267 | I2c_operation_segment_read = 0x02, // not PHY I2C |
paul@65 | 268 | I2c_operation_read = 0x01, |
paul@62 | 269 | }; |
paul@62 | 270 | |
paul@66 | 271 | // Device addresses. |
paul@66 | 272 | |
paul@71 | 273 | enum I2c_phy_device_addresses : uint8_t |
paul@66 | 274 | { |
paul@66 | 275 | I2c_phy_device_phy_gen2 = 0x69, // PHY_I2CM_SLAVE_ADDR_PHY_GEN2 |
paul@66 | 276 | I2c_phy_device_phy_heac = 0x49, // PHY_I2CM_SLAVE_ADDR_HEAC_PHY |
paul@66 | 277 | }; |
paul@66 | 278 | |
paul@66 | 279 | // Device registers. |
paul@66 | 280 | |
paul@71 | 281 | enum I2c_phy_device_registers : uint8_t |
paul@66 | 282 | { |
paul@66 | 283 | I2c_phy_3d_tx_clock_cal_ctrl = 0x05, // 3D_TX_PHY_CKCALCTRL |
paul@66 | 284 | I2c_phy_3d_tx_cpce_ctrl = 0x06, // 3D_TX_PHY_CPCE_CTRL |
paul@66 | 285 | I2c_phy_3d_tx_clock_symbol_ctrl = 0x09, // 3D_TX_PHY_CKSYMTXCTRL |
paul@66 | 286 | I2c_phy_3d_tx_vlevel_ctrl = 0x0e, // 3D_TX_PHY_VLEVCTRL |
paul@66 | 287 | I2c_phy_3d_tx_curr_ctrl = 0x10, // 3D_TX_PHY_CURRCTRL |
paul@66 | 288 | I2c_phy_3d_tx_pll_phby_ctrl = 0x13, // 3D_TX_PHY_PLLPHBYCTRL |
paul@66 | 289 | I2c_phy_3d_tx_gmp_ctrl = 0x15, // 3D_TX_PHY_GMPCTRL |
paul@66 | 290 | I2c_phy_3d_tx_msm_ctrl = 0x17, // 3D_TX_PHY_MSM_CTRL |
paul@66 | 291 | I2c_phy_3d_tx_term = 0x19, // 3D_TX_PHY_TXTERM |
paul@66 | 292 | }; |
paul@66 | 293 | |
paul@66 | 294 | // PHY I2C register values. |
paul@66 | 295 | |
paul@71 | 296 | enum Msm_ctrl_bits : uint16_t |
paul@66 | 297 | { |
paul@66 | 298 | Msm_ctrl_clock_output_select_fb = 1 << 3, // 3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK |
paul@66 | 299 | }; |
paul@66 | 300 | |
paul@71 | 301 | enum Clock_cal_ctrl_bits : uint16_t |
paul@66 | 302 | { |
paul@66 | 303 | Clock_cal_ctrl_override = 1 << 15, // 3D_TX_PHY_CKCALCTRL_OVERRIDE |
paul@66 | 304 | }; |
paul@66 | 305 | |
paul@66 | 306 | // Interrupt configuration bits, also for PHY I2C. |
paul@62 | 307 | |
paul@71 | 308 | enum I2c_int_config0_bits : uint8_t |
paul@62 | 309 | { |
paul@66 | 310 | I2c_int_config0_done_polarity = 0x08, |
paul@66 | 311 | I2c_int_config0_done_mask = 0x04, |
paul@62 | 312 | }; |
paul@62 | 313 | |
paul@71 | 314 | enum I2c_int_config1_bits : uint8_t |
paul@62 | 315 | { |
paul@66 | 316 | I2c_int_config1_nack_polarity = 0x80, |
paul@66 | 317 | I2c_int_config1_nack_mask = 0x40, |
paul@66 | 318 | I2c_int_config1_arb_polarity = 0x08, |
paul@66 | 319 | I2c_int_config1_arb_mask = 0x04, |
paul@65 | 320 | }; |
paul@65 | 321 | |
paul@65 | 322 | // PHY configuration values. |
paul@65 | 323 | |
paul@71 | 324 | enum Phy_config_bits : uint8_t |
paul@65 | 325 | { |
paul@66 | 326 | Phy_config_powerdown_disable = 0x80, // PHY_CONF0_PDZ_MASK |
paul@66 | 327 | Phy_config_tmds = 0x40, // PHY_CONF0_ENTMDS_MASK |
paul@66 | 328 | Phy_config_svsret = 0x20, // PHY_CONF0_SVSRET_MASK |
paul@66 | 329 | Phy_config_gen2_powerdown = 0x10, // PHY_CONF0_GEN2_PDDQ_MASK |
paul@66 | 330 | Phy_config_gen2_tx_power = 0x08, // PHY_CONF0_GEN2_TXPWRON_MASK |
paul@66 | 331 | Phy_config_gen2_hotplug_detect_rx_sense = 0x04, // PHY_CONF0_GEN2_ENHPDRXSENSE_MASK |
paul@66 | 332 | Phy_config_select_data_enable_polarity = 0x02, // PHY_CONF0_SELDATAENPOL_MASK |
paul@66 | 333 | Phy_config_select_interface_control = 0x01, // PHY_CONF0_SELDIPIF_MASK |
paul@65 | 334 | }; |
paul@65 | 335 | |
paul@71 | 336 | enum Phy_test_bits : uint8_t |
paul@65 | 337 | { |
paul@65 | 338 | Phy_test0_clear_mask = 0x20, // PHY_TST0_TSTCLR_MASK |
paul@65 | 339 | Phy_test0_enable_mask = 0x10, // PHY_TST0_TSTEN_MASK |
paul@65 | 340 | Phy_test0_clock_mask = 0x01, // PHY_TST0_TSTCLK_MASK |
paul@65 | 341 | }; |
paul@65 | 342 | |
paul@65 | 343 | // PHY status and mask values. |
paul@65 | 344 | |
paul@71 | 345 | enum Phy_status_bits : uint8_t |
paul@65 | 346 | { |
paul@66 | 347 | Phy_status_all = 0xf3, |
paul@65 | 348 | Phy_status_rx_sense_all = 0xf0, |
paul@65 | 349 | Phy_status_rx_sense3 = 0x80, // PHY_RX_SENSE3 |
paul@65 | 350 | Phy_status_rx_sense2 = 0x40, // PHY_RX_SENSE2 |
paul@65 | 351 | Phy_status_rx_sense1 = 0x20, // PHY_RX_SENSE1 |
paul@65 | 352 | Phy_status_rx_sense0 = 0x10, // PHY_RX_SENSE0 |
paul@65 | 353 | Phy_status_hotplug_detect = 0x02, // PHY_HPD |
paul@65 | 354 | Phy_status_tx_phy_lock = 0x01, // PHY_TX_PHY_LOCK |
paul@66 | 355 | Phy_status_none = 0, |
paul@65 | 356 | }; |
paul@65 | 357 | |
paul@66 | 358 | // PHY interrupt status and mask values. |
paul@65 | 359 | |
paul@71 | 360 | enum Phy_int_status_bits : uint8_t |
paul@65 | 361 | { |
paul@66 | 362 | Phy_int_status_all = 0x3f, |
paul@65 | 363 | Phy_int_status_rx_sense_all = 0x3c, |
paul@65 | 364 | Phy_int_status_rx_sense3 = 0x20, // IH_PHY_STAT0_RX_SENSE3 |
paul@65 | 365 | Phy_int_status_rx_sense2 = 0x10, // IH_PHY_STAT0_RX_SENSE2 |
paul@65 | 366 | Phy_int_status_rx_sense1 = 0x08, // IH_PHY_STAT0_RX_SENSE1 |
paul@65 | 367 | Phy_int_status_rx_sense0 = 0x04, // IH_PHY_STAT0_RX_SENSE0 |
paul@65 | 368 | Phy_int_status_tx_phy_lock = 0x02, // IH_PHY_STAT0_TX_PHY_LOCK |
paul@65 | 369 | Phy_int_status_hotplug_detect = 0x01, // IH_PHY_STAT0_HPD |
paul@66 | 370 | Phy_int_status_none = 0, |
paul@66 | 371 | }; |
paul@66 | 372 | |
paul@66 | 373 | // PHY main register values. |
paul@66 | 374 | |
paul@71 | 375 | enum Main_heac_phy_reset_bits : uint8_t |
paul@66 | 376 | { |
paul@66 | 377 | Main_heac_phy_reset_assert = 0x01, // MC_HEACPHY_RST_ASSERT |
paul@66 | 378 | }; |
paul@66 | 379 | |
paul@71 | 380 | enum Main_flow_control_bits : uint8_t |
paul@66 | 381 | { |
paul@66 | 382 | Main_flow_control_csc_active = 0x01, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH |
paul@66 | 383 | Main_flow_control_csc_inactive = 0x00, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS |
paul@66 | 384 | }; |
paul@66 | 385 | |
paul@71 | 386 | enum Main_clock_disable_bits : uint8_t |
paul@66 | 387 | { |
paul@66 | 388 | Main_clock_disable_hdcp = 0x40, // MC_CLKDIS_HDCPCLK_DISABLE |
paul@66 | 389 | Main_clock_disable_cec = 0x20, // MC_CLKDIS_CECCLK_DISABLE |
paul@66 | 390 | Main_clock_disable_csc = 0x10, // MC_CLKDIS_CSCCLK_DISABLE |
paul@66 | 391 | Main_clock_disable_audio = 0x08, // MC_CLKDIS_AUDCLK_DISABLE |
paul@66 | 392 | Main_clock_disable_prep = 0x04, // MC_CLKDIS_PREPCLK_DISABLE |
paul@66 | 393 | Main_clock_disable_tmds = 0x02, // MC_CLKDIS_TMDSCLK_DISABLE |
paul@66 | 394 | Main_clock_disable_pixel = 0x01, // MC_CLKDIS_PIXELCLK_DISABLE |
paul@66 | 395 | }; |
paul@66 | 396 | |
paul@71 | 397 | enum Main_software_reset_bits : uint8_t |
paul@71 | 398 | { |
paul@71 | 399 | Main_software_reset_tmds = 0x02, // MC_SWRSTZ_TMDSSWRST_REQ |
paul@71 | 400 | }; |
paul@71 | 401 | |
paul@66 | 402 | // Frame composer values. |
paul@66 | 403 | |
paul@71 | 404 | enum Fc_video_config_bits : uint8_t |
paul@66 | 405 | { |
paul@66 | 406 | Fc_video_config_hdcp_keepout_active = 0x80, // FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE |
paul@66 | 407 | Fc_video_config_hdcp_keepout_inactive = 0x00, // FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE |
paul@66 | 408 | Fc_video_config_vsync_active_high = 0x40, // FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH |
paul@66 | 409 | Fc_video_config_vsync_active_low = 0x00, // FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW |
paul@66 | 410 | Fc_video_config_hsync_active_high = 0x20, // FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH |
paul@66 | 411 | Fc_video_config_hsync_active_low = 0x00, // FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW |
paul@66 | 412 | Fc_video_config_data_enable_active_high = 0x10, // FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH |
paul@66 | 413 | Fc_video_config_data_enable_active_low = 0x00, // FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW |
paul@66 | 414 | Fc_video_config_hdmi_mode = 0x08, // FC_INVIDCONF_DVI_MODEZ_HDMI_MODE |
paul@66 | 415 | Fc_video_config_dvi_mode = 0x00, // FC_INVIDCONF_DVI_MODEZ_DVI_MODE |
paul@66 | 416 | Fc_video_config_osc_active_high = 0x02, // FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH |
paul@66 | 417 | Fc_video_config_osc_active_low = 0x00, // FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW |
paul@66 | 418 | Fc_video_config_interlaced = 0x01, // FC_INVIDCONF_IN_I_P_INTERLACED |
paul@66 | 419 | Fc_video_config_progressive = 0x00, // FC_INVIDCONF_IN_I_P_PROGRESSIVE |
paul@66 | 420 | }; |
paul@66 | 421 | |
paul@71 | 422 | enum Fc_int_status2_bits : uint8_t |
paul@66 | 423 | { |
paul@66 | 424 | Fc_int_status2_overflow = 0x03, // FC_STAT2_OVERFLOW_MASK |
paul@66 | 425 | Fc_int_status2_overflow_low = 0x02, // FC_STAT2_LOW_PRIORITY_OVERFLOW |
paul@66 | 426 | Fc_int_status2_overflow_high = 0x01 // FC_STAT2_HIGH_PRIORITY_OVERFLOW, |
paul@66 | 427 | }; |
paul@66 | 428 | |
paul@66 | 429 | // Colour space conversion values. |
paul@66 | 430 | |
paul@71 | 431 | enum Csc_config_bits : uint8_t |
paul@66 | 432 | { |
paul@66 | 433 | Csc_config_interpolation_mask = 0x30, // CSC_CFG_INTMODE_MASK |
paul@66 | 434 | Csc_config_interpolation_disable = 0x00, // CSC_CFG_INTMODE_DISABLE |
paul@66 | 435 | Csc_config_interpolation_form1 = 0x10, // CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 |
paul@66 | 436 | Csc_config_interpolation_form2 = 0x20, // CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 |
paul@66 | 437 | Csc_config_decimation_mask = 0x3, // CSC_CFG_DECMODE_MASK |
paul@66 | 438 | Csc_config_decimation_disable = 0x0, // CSC_CFG_DECMODE_DISABLE |
paul@66 | 439 | Csc_config_decimation_form1 = 0x1, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 |
paul@66 | 440 | Csc_config_decimation_form2 = 0x2, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 |
paul@66 | 441 | Csc_config_decimation_form3 = 0x3, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 |
paul@66 | 442 | }; |
paul@66 | 443 | |
paul@71 | 444 | enum Csc_scale_bits : uint8_t |
paul@66 | 445 | { |
paul@66 | 446 | Csc_scale_colour_depth_mask = 0xf0, // CSC_SCALE_CSC_COLORDE_PTH_MASK |
paul@66 | 447 | Csc_scale_colour_depth_24bpp = 0x00, // CSC_SCALE_CSC_COLORDE_PTH_24BPP |
paul@66 | 448 | Csc_scale_colour_depth_30bpp = 0x50, // CSC_SCALE_CSC_COLORDE_PTH_30BPP |
paul@66 | 449 | Csc_scale_colour_depth_36bpp = 0x60, // CSC_SCALE_CSC_COLORDE_PTH_36BPP |
paul@66 | 450 | Csc_scale_colour_depth_48bpp = 0x70, // CSC_SCALE_CSC_COLORDE_PTH_48BPP |
paul@66 | 451 | Csc_scale_mask = 0x03, // CSC_SCALE_CSCSCALE_MASK |
paul@66 | 452 | }; |
paul@66 | 453 | |
paul@66 | 454 | // HDCP register values. |
paul@66 | 455 | |
paul@71 | 456 | enum Hdcp_config0_bits : uint8_t |
paul@66 | 457 | { |
paul@66 | 458 | Hdcp_config0_rxdetect_enable = 0x4, // A_HDCPCFG0_RXDETECT_ENABLE |
paul@66 | 459 | }; |
paul@66 | 460 | |
paul@71 | 461 | enum Hdcp_config1_bits : uint8_t |
paul@66 | 462 | { |
paul@66 | 463 | Hdcp_config1_encryption_disable = 0x2, // A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE |
paul@66 | 464 | }; |
paul@66 | 465 | |
paul@71 | 466 | enum Hdcp_video_polarity_bits : uint8_t |
paul@66 | 467 | { |
paul@66 | 468 | Hdcp_video_polarity_data_enable_active_high = 0x10, // A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH |
paul@66 | 469 | }; |
paul@66 | 470 | |
paul@66 | 471 | // Video sample register values. |
paul@66 | 472 | |
paul@71 | 473 | enum Sample_video_config_bits : uint8_t |
paul@66 | 474 | { |
paul@66 | 475 | Sample_video_config_data_enable_active = 0x80, // TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE |
paul@66 | 476 | Sample_video_config_mapping_mask = 0x1f, // TX_INVID0_VIDEO_MAPPING_MASK |
paul@66 | 477 | }; |
paul@66 | 478 | |
paul@71 | 479 | enum Sample_video_stuffing_bits : uint8_t |
paul@66 | 480 | { |
paul@66 | 481 | Sample_video_stuffing_bdb_data = 0x04, // TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
paul@66 | 482 | Sample_video_stuffing_rcr_data = 0x02, // TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
paul@66 | 483 | Sample_video_stuffing_gy_data = 0x01, // TX_INSTUFFING_GYDATA_STUFFING_ENABLE |
paul@66 | 484 | }; |
paul@66 | 485 | |
paul@66 | 486 | // Video packetizer register values. |
paul@66 | 487 | |
paul@71 | 488 | enum Packet_stuffing_bits : uint8_t |
paul@66 | 489 | { |
paul@66 | 490 | Packet_stuffing_default_phase = 0x20, // VP_STUFF_IDEFAULT_PHASE_MASK |
paul@66 | 491 | Packet_stuffing_ifix_pp_to_last = 0x10, // VP_STUFF_IFIX_PP_TO_LAST_MASK |
paul@66 | 492 | Packet_stuffing_icx = 0x08, // VP_STUFF_ICX_GOTO_P0_ST_MASK |
paul@66 | 493 | Packet_stuffing_ycc422 = 0x04, // VP_STUFF_YCC422_STUFFING_STUFFING_MODE |
paul@66 | 494 | Packet_stuffing_pp = 0x02, // VP_STUFF_PP_STUFFING_STUFFING_MODE |
paul@66 | 495 | Packet_stuffing_pr = 0x01, // VP_STUFF_PR_STUFFING_STUFFING_MODE |
paul@66 | 496 | }; |
paul@66 | 497 | |
paul@71 | 498 | enum Packet_config_bits : uint8_t |
paul@66 | 499 | { |
paul@66 | 500 | Packet_config_bypass_enable = 0x40, // VP_CONF_BYPASS_EN_ENABLE |
paul@66 | 501 | Packet_config_pp_enable = 0x20, // VP_CONF_PP_EN_ENABLE |
paul@66 | 502 | Packet_config_pr_enable = 0x10, // VP_CONF_PR_EN_ENABLE |
paul@66 | 503 | Packet_config_ycc422_enable = 0x8, // VP_CONF_YCC422_EN_ENABLE |
paul@66 | 504 | Packet_config_bypass_select_packetizer = 0x4, // VP_CONF_BYPASS_SELECT_VID_PACKETIZER |
paul@66 | 505 | Packet_config_output_selector_mask = 0x3, // VP_CONF_OUTPUT_SELECTOR_MASK |
paul@66 | 506 | Packet_config_output_selector_bypass = 0x3, // VP_CONF_OUTPUT_SELECTOR_BYPASS |
paul@66 | 507 | Packet_config_output_selector_ycc422 = 0x1, // VP_CONF_OUTPUT_SELECTOR_YCC422 |
paul@66 | 508 | Packet_config_output_selector_pp = 0x0, // VP_CONF_OUTPUT_SELECTOR_PP |
paul@66 | 509 | }; |
paul@66 | 510 | |
paul@71 | 511 | enum Packet_remap_bits : uint8_t |
paul@66 | 512 | { |
paul@66 | 513 | Packet_remap_mask = 0x3, // VP_REMAP_MASK |
paul@66 | 514 | Packet_remap_ycc422_24bit = 0x2, // VP_REMAP_YCC422_24bit |
paul@66 | 515 | Packet_remap_ycc422_20bit = 0x1, // VP_REMAP_YCC422_20bit |
paul@66 | 516 | Packet_remap_ycc422_16bit = 0x0, // VP_REMAP_YCC422_16bit |
paul@66 | 517 | }; |
paul@66 | 518 | |
paul@71 | 519 | enum Packet_pr_cd_bits : uint8_t |
paul@66 | 520 | { |
paul@71 | 521 | Packet_pr_cd_depth_mask = 0xf0, // VP_PR_CD_COLOR_DEPTH_MASK |
paul@71 | 522 | Packet_pr_cd_depth_offset = 4, // VP_PR_CD_COLOR_DEPTH_OFFSET |
paul@71 | 523 | Packet_pr_cd_factor_mask = 0x0f, // VP_PR_CD_DESIRED_PR_FACTOR_MASK |
paul@71 | 524 | Packet_pr_cd_factor_offset = 0, // VP_PR_CD_DESIRED_PR_FACTOR_OFFSET |
paul@66 | 525 | }; |
paul@66 | 526 | |
paul@66 | 527 | |
paul@66 | 528 | |
paul@66 | 529 | // PHY capabilities. |
paul@66 | 530 | |
paul@66 | 531 | static const Phy_capabilities phy_capabilities[] = { |
paul@66 | 532 | // name gen svsret configure |
paul@66 | 533 | {Config2_dwc_hdmi_tx_phy, "DWC_HDMI_TX_PHY", 1, false, false}, |
paul@66 | 534 | {Config2_dwc_mhl_phy_heac, "DWC_MHL_PHY_HEAC", 2, true, true}, |
paul@66 | 535 | {Config2_dwc_mhl_phy, "DWC_MHL_PHY", 2, true, true}, |
paul@66 | 536 | {Config2_dwc_hdmi_3d_tx_phy_heac, "DWC_HDMI_3D_TX_PHY_HEAC", 2, false, true}, |
paul@66 | 537 | {Config2_dwc_hdmi_3d_tx_phy, "DWC_HDMI_3D_TX_PHY", 2, false, true}, |
paul@66 | 538 | {Config2_dwc_hdmi20_tx_phy, "DWC_HDMI20_TX_PHY", 2, true, true}, |
paul@66 | 539 | {0, "Vendor PHY", 0, false, false}, |
paul@66 | 540 | }; |
paul@66 | 541 | |
paul@66 | 542 | |
paul@66 | 543 | |
paul@66 | 544 | // PHY configuration, adopting the Linux driver's tables of values. |
paul@66 | 545 | |
paul@66 | 546 | static const struct Phy_mpll_config phy_mpll_config[] = { |
paul@66 | 547 | // 8bpc 10bpc 12bpc |
paul@66 | 548 | // pixelclock cpce gmp cpce gmp cpce gmp |
paul@66 | 549 | { 45250000, { {0x01e0, 0x0000}, {0x21e1, 0x0000}, {0x41e2, 0x0000} } }, |
paul@66 | 550 | { 92500000, { {0x0140, 0x0005}, {0x2141, 0x0005}, {0x4142, 0x0005} } }, |
paul@66 | 551 | { 148500000, { {0x00a0, 0x000a}, {0x20a1, 0x000a}, {0x40a2, 0x000a} } }, |
paul@66 | 552 | { 216000000, { {0x00a0, 0x000a}, {0x2001, 0x000f}, {0x4002, 0x000f} } }, |
paul@66 | 553 | { ~0UL, { {0x0000, 0x0000}, {0x0000, 0x0000}, {0x0000, 0x0000} } } |
paul@66 | 554 | }; |
paul@66 | 555 | |
paul@66 | 556 | static const struct Phy_curr_ctrl phy_curr_ctrl[] = { |
paul@66 | 557 | // pixelclock 8bpc 10bpc 12bpc |
paul@66 | 558 | { 54000000, {0x091c, 0x091c, 0x06dc} }, |
paul@66 | 559 | { 58400000, {0x091c, 0x06dc, 0x06dc} }, |
paul@66 | 560 | { 72000000, {0x06dc, 0x06dc, 0x091c} }, |
paul@66 | 561 | { 74250000, {0x06dc, 0x0b5c, 0x091c} }, |
paul@66 | 562 | { 118800000, {0x091c, 0x091c, 0x06dc} }, |
paul@66 | 563 | { 216000000, {0x06dc, 0x0b5c, 0x091c} }, |
paul@66 | 564 | { ~0UL, {0x0000, 0x0000, 0x0000} } |
paul@66 | 565 | }; |
paul@66 | 566 | |
paul@66 | 567 | static const struct Phy_config phy_config[] = { |
paul@66 | 568 | // pixelclock symbol term vlevel |
paul@66 | 569 | { 216000000, 0x800d, 0x0005, 0x01ad}, |
paul@66 | 570 | { ~0UL, 0x0000, 0x0000, 0x0000} |
paul@62 | 571 | }; |
paul@62 | 572 | |
paul@62 | 573 | |
paul@62 | 574 | |
paul@62 | 575 | // Initialise the HDMI peripheral. |
paul@62 | 576 | |
paul@62 | 577 | Hdmi_jz4780_chip::Hdmi_jz4780_chip(l4_addr_t start, l4_addr_t end, |
paul@66 | 578 | l4_cap_idx_t irq, |
paul@66 | 579 | struct Jz4740_lcd_panel *panel) |
paul@66 | 580 | : _start(start), _end(end), _irq(irq), _panel(panel) |
paul@62 | 581 | { |
paul@62 | 582 | // 8-bit registers with 2-bit address shifting. |
paul@62 | 583 | |
paul@62 | 584 | _regs = new Hw::Mmio_register_block<8>(start, 2); |
paul@62 | 585 | |
paul@66 | 586 | // Initialise I2C state for DDC. |
paul@66 | 587 | |
paul@62 | 588 | _segment_read = false; |
paul@62 | 589 | _device_register = 0; |
paul@62 | 590 | |
paul@66 | 591 | // Initialise I2C state for PHY initialisation. |
paul@66 | 592 | |
paul@66 | 593 | _phy_device_register = 0; |
paul@66 | 594 | |
paul@66 | 595 | // Initialise identifying details and capabilities of the hardware. |
paul@66 | 596 | |
paul@62 | 597 | get_identification(); |
paul@66 | 598 | |
paul@66 | 599 | // Reset interrupts to a minimal, enabled state. |
paul@66 | 600 | |
paul@65 | 601 | irq_init(); |
paul@66 | 602 | |
paul@66 | 603 | // Set up DDC and PHY communication. |
paul@66 | 604 | |
paul@66 | 605 | i2c_init(I2c_software_reset, I2c_divider, I2c_int_config0, I2c_int_config1, |
paul@66 | 606 | I2c_int_status, I2c_int_mask); |
paul@66 | 607 | i2c_init(I2c_phy_software_reset, I2c_phy_divider, I2c_phy_int_config0, I2c_phy_int_config1, |
paul@66 | 608 | I2c_phy_int_status, I2c_phy_int_mask); |
paul@66 | 609 | |
paul@66 | 610 | // Enable PHY interrupts. |
paul@66 | 611 | |
paul@66 | 612 | phy_irq_init(); |
paul@66 | 613 | } |
paul@66 | 614 | |
paul@66 | 615 | // Pixel clock frequency calculation. |
paul@66 | 616 | |
paul@66 | 617 | unsigned long Hdmi_jz4780_chip::get_pixelclock() |
paul@66 | 618 | { |
paul@66 | 619 | return _pixelclock; |
paul@66 | 620 | |
paul@66 | 621 | /* Calculated frequency, which may not be the actual pixelclock frequency... |
paul@66 | 622 | |
paul@66 | 623 | return (_panel->line_start + _panel->width + _panel->line_end + _panel->hsync) * |
paul@66 | 624 | (_panel->frame_start + _panel->height + _panel->frame_end + _panel->vsync) * |
paul@66 | 625 | _panel->frame_rate; |
paul@66 | 626 | */ |
paul@62 | 627 | } |
paul@62 | 628 | |
paul@66 | 629 | |
paul@66 | 630 | |
paul@66 | 631 | // Update a register by enabling/setting or disabling/clearing the given bits. |
paul@66 | 632 | |
paul@66 | 633 | void Hdmi_jz4780_chip::reg_update(uint32_t reg, uint32_t bits, bool enable) |
paul@66 | 634 | { |
paul@66 | 635 | if (enable) |
paul@66 | 636 | _regs[reg] = _regs[reg] | bits; |
paul@66 | 637 | else |
paul@66 | 638 | _regs[reg] = _regs[reg] & ~bits; |
paul@66 | 639 | } |
paul@66 | 640 | |
paul@66 | 641 | // Update a field. The bits must be shifted to coincide with the mask. |
paul@66 | 642 | |
paul@66 | 643 | void Hdmi_jz4780_chip::reg_update_field(uint32_t reg, uint32_t mask, uint32_t bits) |
paul@66 | 644 | { |
paul@66 | 645 | _regs[reg] = (_regs[reg] & ~(mask)) | (bits & mask); |
paul@66 | 646 | } |
paul@66 | 647 | |
paul@66 | 648 | void Hdmi_jz4780_chip::reg_fill_field(uint32_t reg, uint32_t mask) |
paul@66 | 649 | { |
paul@66 | 650 | _regs[reg] = _regs[reg] | mask; |
paul@66 | 651 | } |
paul@66 | 652 | |
paul@66 | 653 | |
paul@66 | 654 | |
paul@66 | 655 | // Chipset querying. |
paul@66 | 656 | |
paul@62 | 657 | void Hdmi_jz4780_chip::get_identification() |
paul@62 | 658 | { |
paul@62 | 659 | _version = (_regs[Design_id] << 8) | _regs[Revision_id]; |
paul@66 | 660 | _phy_type = _regs[Config_id2]; |
paul@66 | 661 | |
paul@66 | 662 | // Initialise a member to any matching capabilities or leave it as the "null" |
paul@66 | 663 | // entry. |
paul@66 | 664 | |
paul@66 | 665 | _phy_def = phy_capabilities; |
paul@66 | 666 | |
paul@66 | 667 | while (_phy_def->gen && (_phy_def->type != _phy_type)) |
paul@66 | 668 | _phy_def++; |
paul@62 | 669 | } |
paul@62 | 670 | |
paul@62 | 671 | void Hdmi_jz4780_chip::get_version(uint8_t *major, uint16_t *minor) |
paul@62 | 672 | { |
paul@66 | 673 | *major = (_version >> 12) & 0xfff; |
paul@62 | 674 | *minor = _version & 0xfff; |
paul@62 | 675 | } |
paul@62 | 676 | |
paul@66 | 677 | void Hdmi_jz4780_chip::get_phy_capabilities(const struct Phy_capabilities **phy_def) |
paul@66 | 678 | { |
paul@66 | 679 | *phy_def = _phy_def; |
paul@66 | 680 | } |
paul@66 | 681 | |
paul@66 | 682 | |
paul@66 | 683 | |
paul@66 | 684 | // Initialisation. |
paul@66 | 685 | |
paul@65 | 686 | void Hdmi_jz4780_chip::irq_init() |
paul@62 | 687 | { |
paul@62 | 688 | // Disable interrupts. |
paul@62 | 689 | |
paul@62 | 690 | _regs[Int_mask] = _regs[Int_mask] | (Int_mask_wakeup | Int_mask_all); |
paul@62 | 691 | |
paul@62 | 692 | // Mask all interrupts. |
paul@62 | 693 | |
paul@62 | 694 | _regs[Fc_int_mask0] = 0xff; |
paul@62 | 695 | _regs[Fc_int_mask1] = 0xff; |
paul@62 | 696 | _regs[Fc_int_mask2] = 0xff; |
paul@62 | 697 | _regs[As_int_mask] = 0xff; |
paul@62 | 698 | _regs[Phy_int_mask] = 0xff; |
paul@62 | 699 | _regs[I2c_int_mask] = 0xff; |
paul@66 | 700 | _regs[I2c_phy_int_mask] = 0xff; |
paul@62 | 701 | _regs[Cec_int_mask] = 0xff; |
paul@62 | 702 | _regs[Vp_int_mask] = 0xff; |
paul@62 | 703 | _regs[Ahb_dma_audio_int_mask] = 0xff; |
paul@62 | 704 | |
paul@62 | 705 | // Enable interrupts. |
paul@62 | 706 | |
paul@62 | 707 | _regs[Int_mask] = _regs[Int_mask] & ~(Int_mask_wakeup | Int_mask_all); |
paul@62 | 708 | } |
paul@62 | 709 | |
paul@66 | 710 | void Hdmi_jz4780_chip::phy_irq_init() |
paul@62 | 711 | { |
paul@65 | 712 | // Set PHY interrupt polarities. |
paul@62 | 713 | |
paul@66 | 714 | _regs[Phy_polarity] = Phy_status_all; |
paul@66 | 715 | |
paul@66 | 716 | // Enable/unmask second-level interrupts. |
paul@66 | 717 | |
paul@66 | 718 | _regs[Phy_mask] = _regs[Phy_mask] & ~(Phy_status_all); |
paul@66 | 719 | |
paul@66 | 720 | // Clear pending interrupts. |
paul@66 | 721 | |
paul@66 | 722 | _regs[Phy_int_status] = Phy_int_status_all; |
paul@66 | 723 | |
paul@66 | 724 | // Enable/unmask interrupts. |
paul@62 | 725 | |
paul@66 | 726 | _regs[Phy_int_mask] = _regs[Phy_int_mask] & ~(Phy_int_status_all); |
paul@66 | 727 | } |
paul@66 | 728 | |
paul@66 | 729 | |
paul@66 | 730 | |
paul@66 | 731 | // I2C support. |
paul@66 | 732 | |
paul@66 | 733 | void Hdmi_jz4780_chip::i2c_init(uint32_t reset, uint32_t divider, |
paul@66 | 734 | uint32_t config0, uint32_t config1, |
paul@66 | 735 | uint32_t status, uint32_t mask) |
paul@66 | 736 | { |
paul@62 | 737 | // Software reset. |
paul@62 | 738 | |
paul@66 | 739 | _regs[reset] = 0; |
paul@62 | 740 | |
paul@62 | 741 | // Standard mode (100kHz). |
paul@62 | 742 | |
paul@66 | 743 | _regs[divider] = 0; |
paul@62 | 744 | |
paul@62 | 745 | // Set interrupt polarities. |
paul@62 | 746 | |
paul@66 | 747 | _regs[config0] = I2c_int_config0_done_polarity; |
paul@66 | 748 | _regs[config1] = I2c_int_config1_nack_polarity | I2c_int_config1_arb_polarity; |
paul@62 | 749 | |
paul@62 | 750 | // Clear and mask/mute interrupts. |
paul@62 | 751 | |
paul@66 | 752 | _regs[status] = I2c_int_status_done | I2c_int_status_error; |
paul@66 | 753 | _regs[mask] = I2c_int_status_done | I2c_int_status_error; |
paul@62 | 754 | } |
paul@62 | 755 | |
paul@66 | 756 | long Hdmi_jz4780_chip::i2c_wait(uint32_t status) |
paul@62 | 757 | { |
paul@62 | 758 | long err; |
paul@65 | 759 | uint8_t int_status; |
paul@65 | 760 | l4_msgtag_t tag; |
paul@62 | 761 | |
paul@65 | 762 | do |
paul@65 | 763 | { |
paul@65 | 764 | tag = l4_irq_receive(_irq, L4_IPC_NEVER); |
paul@62 | 765 | |
paul@65 | 766 | err = l4_ipc_error(tag, l4_utcb()); |
paul@65 | 767 | if (err) |
paul@65 | 768 | return err; |
paul@62 | 769 | |
paul@66 | 770 | int_status = _regs[status]; |
paul@65 | 771 | |
paul@65 | 772 | // Test for an error condition. |
paul@62 | 773 | |
paul@65 | 774 | if (int_status & I2c_int_status_error) |
paul@65 | 775 | return -L4_EIO; |
paul@62 | 776 | |
paul@65 | 777 | // Acknowledge the interrupt. |
paul@62 | 778 | |
paul@66 | 779 | _regs[status] = int_status; |
paul@65 | 780 | |
paul@65 | 781 | } while (!(int_status & I2c_int_status_done)); |
paul@62 | 782 | |
paul@62 | 783 | return L4_EOK; |
paul@62 | 784 | } |
paul@62 | 785 | |
paul@62 | 786 | int Hdmi_jz4780_chip::i2c_read(uint8_t *buf, unsigned int length) |
paul@62 | 787 | { |
paul@62 | 788 | unsigned int i; |
paul@62 | 789 | long err; |
paul@62 | 790 | |
paul@65 | 791 | // Unmask interrupts. |
paul@62 | 792 | |
paul@62 | 793 | _regs[I2c_int_mask] = 0; |
paul@62 | 794 | |
paul@62 | 795 | for (i = 0; i < length; i++) |
paul@62 | 796 | { |
paul@62 | 797 | // Increment the device register. |
paul@62 | 798 | |
paul@62 | 799 | _regs[I2c_register] = _device_register++; |
paul@62 | 800 | _regs[I2c_operation] = _segment_read ? I2c_operation_segment_read |
paul@62 | 801 | : I2c_operation_read; |
paul@62 | 802 | |
paul@62 | 803 | // Wait and then read. |
paul@62 | 804 | |
paul@66 | 805 | err = i2c_wait(I2c_int_status); |
paul@62 | 806 | if (err) |
paul@62 | 807 | break; |
paul@62 | 808 | |
paul@62 | 809 | buf[i] = _regs[I2c_data_in]; |
paul@62 | 810 | } |
paul@62 | 811 | |
paul@62 | 812 | // Mask interrupts again. |
paul@62 | 813 | |
paul@62 | 814 | _regs[I2c_int_mask] = I2c_int_status_done | I2c_int_status_error; |
paul@62 | 815 | |
paul@62 | 816 | return i; |
paul@62 | 817 | } |
paul@62 | 818 | |
paul@66 | 819 | int Hdmi_jz4780_chip::i2c_phy_write(uint8_t address, uint16_t value) |
paul@66 | 820 | { |
paul@66 | 821 | i2c_phy_set_address(address); |
paul@66 | 822 | return i2c_phy_write(&value, 1); |
paul@66 | 823 | } |
paul@66 | 824 | |
paul@66 | 825 | int Hdmi_jz4780_chip::i2c_phy_write(uint16_t *buf, unsigned int length) |
paul@66 | 826 | { |
paul@66 | 827 | unsigned int i; |
paul@66 | 828 | long err; |
paul@66 | 829 | |
paul@66 | 830 | // Unmask interrupts. |
paul@66 | 831 | |
paul@66 | 832 | _regs[I2c_phy_int_mask] = 0; |
paul@66 | 833 | |
paul@66 | 834 | for (i = 0; i < length; i++) |
paul@66 | 835 | { |
paul@66 | 836 | // Increment the device register. |
paul@66 | 837 | |
paul@66 | 838 | _regs[I2c_phy_register] = _device_register++; |
paul@66 | 839 | _regs[I2c_phy_operation] = I2c_operation_write; |
paul@66 | 840 | |
paul@66 | 841 | // Write and then wait. |
paul@66 | 842 | |
paul@66 | 843 | _regs[I2c_phy_data_out1] = (buf[i] >> 8) & 0xff; |
paul@66 | 844 | _regs[I2c_phy_data_out0] = buf[i] & 0xff; |
paul@66 | 845 | |
paul@66 | 846 | err = i2c_wait(I2c_phy_int_status); |
paul@66 | 847 | if (err) |
paul@66 | 848 | break; |
paul@66 | 849 | } |
paul@66 | 850 | |
paul@66 | 851 | // Mask interrupts again. |
paul@66 | 852 | |
paul@66 | 853 | _regs[I2c_phy_int_mask] = I2c_int_status_done | I2c_int_status_error; |
paul@66 | 854 | |
paul@66 | 855 | return i; |
paul@66 | 856 | } |
paul@66 | 857 | |
paul@62 | 858 | void Hdmi_jz4780_chip::i2c_set_address(uint8_t address) |
paul@62 | 859 | { |
paul@62 | 860 | _regs[I2c_device_address] = address; |
paul@62 | 861 | _segment_read = false; |
paul@62 | 862 | i2c_set_register(0); |
paul@62 | 863 | } |
paul@62 | 864 | |
paul@66 | 865 | void Hdmi_jz4780_chip::i2c_phy_set_address(uint8_t address) |
paul@66 | 866 | { |
paul@66 | 867 | // The Linux drivers seem to set the clear field when changing the PHY device |
paul@66 | 868 | // address, presumably because some manual says so. |
paul@66 | 869 | |
paul@66 | 870 | _regs[Phy_test0] = _regs[Phy_test0] | Phy_test0_clear_mask; |
paul@66 | 871 | _regs[I2c_phy_device_address] = address; |
paul@66 | 872 | _regs[Phy_test0] = _regs[Phy_test0] & ~Phy_test0_clear_mask; |
paul@66 | 873 | |
paul@66 | 874 | i2c_phy_set_register(0); |
paul@66 | 875 | } |
paul@66 | 876 | |
paul@62 | 877 | void Hdmi_jz4780_chip::i2c_set_segment(uint8_t segment) |
paul@62 | 878 | { |
paul@62 | 879 | _regs[I2c_segment_address] = 0x30; |
paul@62 | 880 | _regs[I2c_segment_pointer] = segment; |
paul@62 | 881 | _segment_read = true; |
paul@62 | 882 | i2c_set_register(0); |
paul@62 | 883 | } |
paul@62 | 884 | |
paul@62 | 885 | void Hdmi_jz4780_chip::i2c_set_register(uint8_t device_register) |
paul@62 | 886 | { |
paul@62 | 887 | _device_register = device_register; |
paul@62 | 888 | } |
paul@62 | 889 | |
paul@66 | 890 | void Hdmi_jz4780_chip::i2c_phy_set_register(uint8_t device_register) |
paul@66 | 891 | { |
paul@66 | 892 | _phy_device_register = device_register; |
paul@66 | 893 | } |
paul@66 | 894 | |
paul@66 | 895 | |
paul@66 | 896 | |
paul@66 | 897 | // PHY operations. |
paul@66 | 898 | |
paul@66 | 899 | void Hdmi_jz4780_chip::phy_enable_powerdown(bool enable) |
paul@66 | 900 | { |
paul@66 | 901 | reg_update(Phy_config, Phy_config_powerdown_disable, !enable); |
paul@66 | 902 | } |
paul@66 | 903 | |
paul@66 | 904 | void Hdmi_jz4780_chip::phy_enable_tmds(bool enable) |
paul@66 | 905 | { |
paul@66 | 906 | reg_update(Phy_config, Phy_config_tmds, enable); |
paul@66 | 907 | } |
paul@66 | 908 | |
paul@66 | 909 | void Hdmi_jz4780_chip::phy_enable_svsret(bool enable) |
paul@65 | 910 | { |
paul@66 | 911 | reg_update(Phy_config, Phy_config_svsret, enable); |
paul@66 | 912 | } |
paul@66 | 913 | |
paul@66 | 914 | void Hdmi_jz4780_chip::phy_enable_gen2_powerdown(bool enable) |
paul@66 | 915 | { |
paul@66 | 916 | reg_update(Phy_config, Phy_config_gen2_powerdown, enable); |
paul@66 | 917 | } |
paul@66 | 918 | |
paul@66 | 919 | void Hdmi_jz4780_chip::phy_enable_gen2_tx_power(bool enable) |
paul@66 | 920 | { |
paul@66 | 921 | reg_update(Phy_config, Phy_config_gen2_tx_power, enable); |
paul@66 | 922 | } |
paul@66 | 923 | |
paul@66 | 924 | void Hdmi_jz4780_chip::phy_enable_interface(bool enable) |
paul@66 | 925 | { |
paul@66 | 926 | reg_update(Phy_config, Phy_config_select_data_enable_polarity, enable); |
paul@66 | 927 | reg_update(Phy_config, Phy_config_select_interface_control, !enable); |
paul@66 | 928 | } |
paul@66 | 929 | |
paul@66 | 930 | // Configure the PHY. Various things not supported by the JZ4780 PHY are ignored |
paul@66 | 931 | // such as the TDMS clock ratio (dependent on HDMI 2 and content scrambling). |
paul@66 | 932 | |
paul@66 | 933 | long Hdmi_jz4780_chip::phy_configure() |
paul@66 | 934 | { |
paul@66 | 935 | long err; |
paul@65 | 936 | |
paul@66 | 937 | phy_power_off(); |
paul@66 | 938 | |
paul@66 | 939 | if (_phy_def->svsret) |
paul@66 | 940 | phy_enable_svsret(true); |
paul@66 | 941 | |
paul@66 | 942 | phy_reset(); |
paul@66 | 943 | |
paul@66 | 944 | _regs[Main_heac_phy_reset] = Main_heac_phy_reset_assert; |
paul@66 | 945 | |
paul@66 | 946 | i2c_phy_set_address(I2c_phy_device_phy_gen2); |
paul@66 | 947 | |
paul@66 | 948 | if (_phy_def->configure) |
paul@66 | 949 | { |
paul@66 | 950 | err = phy_configure_specific(); |
paul@66 | 951 | if (err) |
paul@66 | 952 | return err; |
paul@66 | 953 | } |
paul@66 | 954 | |
paul@66 | 955 | // NOTE: TMDS clock delay here in Linux driver. |
paul@66 | 956 | |
paul@66 | 957 | phy_power_on(); |
paul@65 | 958 | |
paul@66 | 959 | return L4_EOK; |
paul@66 | 960 | } |
paul@66 | 961 | |
paul@66 | 962 | // Configure for the JZ4780 specifically. |
paul@66 | 963 | |
paul@66 | 964 | long Hdmi_jz4780_chip::phy_configure_specific() |
paul@66 | 965 | { |
paul@66 | 966 | const struct Phy_mpll_config *m = phy_mpll_config; |
paul@66 | 967 | const struct Phy_curr_ctrl *c = phy_curr_ctrl; |
paul@66 | 968 | const struct Phy_config *p = phy_config; |
paul@66 | 969 | unsigned long pixelclock = get_pixelclock(); |
paul@66 | 970 | |
paul@66 | 971 | // Find MPLL, CURR_CTRL and PHY configuration settings appropriate for the |
paul@66 | 972 | // pixel clock frequency. |
paul@66 | 973 | |
paul@66 | 974 | while (m->pixelclock && (pixelclock > m->pixelclock)) |
paul@66 | 975 | m++; |
paul@66 | 976 | |
paul@66 | 977 | while (c->pixelclock && (pixelclock > c->pixelclock)) |
paul@66 | 978 | c++; |
paul@66 | 979 | |
paul@66 | 980 | while (p->pixelclock && (pixelclock > p->pixelclock)) |
paul@66 | 981 | p++; |
paul@66 | 982 | |
paul@66 | 983 | if (!m->pixelclock || !c->pixelclock || !p->pixelclock) |
paul@66 | 984 | return -L4_EINVAL; |
paul@66 | 985 | |
paul@66 | 986 | // Using values for 8bpc from the tables. |
paul@66 | 987 | |
paul@66 | 988 | // Initialise MPLL. |
paul@66 | 989 | |
paul@66 | 990 | i2c_phy_write(I2c_phy_3d_tx_cpce_ctrl, m->res[Phy_resolution_8bpc].cpce); |
paul@66 | 991 | i2c_phy_write(I2c_phy_3d_tx_gmp_ctrl, m->res[Phy_resolution_8bpc].gmp); |
paul@66 | 992 | |
paul@66 | 993 | // Initialise CURRCTRL. |
paul@66 | 994 | |
paul@66 | 995 | i2c_phy_write(I2c_phy_3d_tx_cpce_ctrl, c->curr[Phy_resolution_8bpc]); |
paul@66 | 996 | |
paul@66 | 997 | // Initialise PHY_CONFIG. |
paul@66 | 998 | |
paul@66 | 999 | i2c_phy_write(I2c_phy_3d_tx_pll_phby_ctrl, 0); |
paul@66 | 1000 | i2c_phy_write(I2c_phy_3d_tx_msm_ctrl, Msm_ctrl_clock_output_select_fb); |
paul@66 | 1001 | |
paul@66 | 1002 | i2c_phy_write(I2c_phy_3d_tx_term, p->term); |
paul@66 | 1003 | i2c_phy_write(I2c_phy_3d_tx_clock_symbol_ctrl, p->symbol); |
paul@66 | 1004 | i2c_phy_write(I2c_phy_3d_tx_vlevel_ctrl, p->vlevel); |
paul@65 | 1005 | |
paul@66 | 1006 | // Override and disable clock termination. |
paul@66 | 1007 | |
paul@66 | 1008 | i2c_phy_write(I2c_phy_3d_tx_clock_cal_ctrl, Clock_cal_ctrl_override); |
paul@66 | 1009 | |
paul@66 | 1010 | return L4_EOK; |
paul@66 | 1011 | } |
paul@66 | 1012 | |
paul@66 | 1013 | long Hdmi_jz4780_chip::phy_init() |
paul@66 | 1014 | { |
paul@66 | 1015 | long err; |
paul@66 | 1016 | int i; |
paul@66 | 1017 | |
paul@66 | 1018 | // Initialisation repeated for HDMI PHY specification reasons. |
paul@66 | 1019 | |
paul@66 | 1020 | for (i = 0; i < 2; i++) |
paul@66 | 1021 | { |
paul@66 | 1022 | phy_enable_interface(true); |
paul@66 | 1023 | err = phy_configure(); |
paul@66 | 1024 | if (err) |
paul@66 | 1025 | return err; |
paul@66 | 1026 | } |
paul@65 | 1027 | |
paul@66 | 1028 | return L4_EOK; |
paul@66 | 1029 | } |
paul@66 | 1030 | |
paul@66 | 1031 | void Hdmi_jz4780_chip::phy_reset() |
paul@66 | 1032 | { |
paul@66 | 1033 | _regs[Main_reset] = 1; |
paul@66 | 1034 | _regs[Main_reset] = 0; |
paul@66 | 1035 | } |
paul@66 | 1036 | |
paul@66 | 1037 | void Hdmi_jz4780_chip::phy_power_off() |
paul@66 | 1038 | { |
paul@66 | 1039 | if (_phy_def && (_phy_def->gen == 1)) |
paul@66 | 1040 | { |
paul@66 | 1041 | phy_enable_tmds(false); |
paul@66 | 1042 | phy_enable_powerdown(true); |
paul@66 | 1043 | return; |
paul@66 | 1044 | } |
paul@66 | 1045 | |
paul@66 | 1046 | phy_enable_gen2_tx_power(false); |
paul@66 | 1047 | |
paul@66 | 1048 | wait_for_tx_phy_lock(0); |
paul@65 | 1049 | |
paul@66 | 1050 | phy_enable_gen2_powerdown(true); |
paul@66 | 1051 | } |
paul@66 | 1052 | |
paul@66 | 1053 | void Hdmi_jz4780_chip::phy_power_on() |
paul@66 | 1054 | { |
paul@66 | 1055 | if (_phy_def && (_phy_def->gen == 1)) |
paul@66 | 1056 | { |
paul@66 | 1057 | phy_enable_powerdown(false); |
paul@66 | 1058 | phy_enable_tmds(false); |
paul@66 | 1059 | phy_enable_tmds(true); |
paul@66 | 1060 | return; |
paul@66 | 1061 | } |
paul@66 | 1062 | |
paul@66 | 1063 | phy_enable_gen2_tx_power(true); |
paul@66 | 1064 | phy_enable_gen2_powerdown(false); |
paul@66 | 1065 | |
paul@66 | 1066 | wait_for_tx_phy_lock(1); |
paul@65 | 1067 | } |
paul@65 | 1068 | |
paul@66 | 1069 | |
paul@66 | 1070 | |
paul@66 | 1071 | // Hotplug detection. |
paul@66 | 1072 | |
paul@65 | 1073 | bool Hdmi_jz4780_chip::connected() |
paul@65 | 1074 | { |
paul@65 | 1075 | return (_regs[Phy_status] & Phy_status_hotplug_detect) != 0; |
paul@65 | 1076 | } |
paul@65 | 1077 | |
paul@65 | 1078 | long Hdmi_jz4780_chip::wait_for_connection() |
paul@65 | 1079 | { |
paul@66 | 1080 | return wait_for_phy_irq(Phy_int_status_hotplug_detect, Phy_status_hotplug_detect, |
paul@66 | 1081 | Phy_status_hotplug_detect); |
paul@66 | 1082 | } |
paul@66 | 1083 | |
paul@66 | 1084 | // General PHY interrupt handling. |
paul@66 | 1085 | |
paul@66 | 1086 | long Hdmi_jz4780_chip::wait_for_phy_irq(uint32_t int_status_flags, |
paul@66 | 1087 | uint32_t status_flags, |
paul@66 | 1088 | uint32_t status_values) |
paul@66 | 1089 | { |
paul@65 | 1090 | long err; |
paul@66 | 1091 | uint8_t int_status, status; |
paul@66 | 1092 | uint8_t status_unchanged = ~(status_values) & status_flags; |
paul@65 | 1093 | l4_msgtag_t tag; |
paul@65 | 1094 | |
paul@65 | 1095 | do |
paul@65 | 1096 | { |
paul@65 | 1097 | tag = l4_irq_receive(_irq, L4_IPC_NEVER); |
paul@65 | 1098 | |
paul@65 | 1099 | err = l4_ipc_error(tag, l4_utcb()); |
paul@65 | 1100 | if (err) |
paul@65 | 1101 | return err; |
paul@65 | 1102 | |
paul@65 | 1103 | // Obtain the details. |
paul@65 | 1104 | |
paul@65 | 1105 | int_status = _regs[Phy_int_status]; |
paul@66 | 1106 | status = _regs[Phy_status]; |
paul@65 | 1107 | |
paul@65 | 1108 | // Acknowledge the interrupt. |
paul@65 | 1109 | |
paul@66 | 1110 | _regs[Phy_int_status] = int_status_flags; |
paul@66 | 1111 | |
paul@66 | 1112 | // Continue without a handled event. |
paul@66 | 1113 | // An event is handled when detected and when the status differs from |
paul@66 | 1114 | // the unchanged state. |
paul@66 | 1115 | |
paul@66 | 1116 | } while (!((int_status & int_status_flags) && |
paul@66 | 1117 | ((status & status_flags) ^ status_unchanged))); |
paul@66 | 1118 | |
paul@66 | 1119 | return L4_EOK; |
paul@66 | 1120 | } |
paul@66 | 1121 | |
paul@66 | 1122 | // Wait for TX_PHY_LOCK to become high or low. |
paul@66 | 1123 | |
paul@66 | 1124 | long Hdmi_jz4780_chip::wait_for_tx_phy_lock(int level) |
paul@66 | 1125 | { |
paul@66 | 1126 | if (!!(_regs[Phy_status] & Phy_status_tx_phy_lock) == level) |
paul@66 | 1127 | return L4_EOK; |
paul@66 | 1128 | |
paul@66 | 1129 | return wait_for_phy_irq(Phy_int_status_tx_phy_lock, Phy_status_tx_phy_lock, |
paul@66 | 1130 | level ? Phy_status_tx_phy_lock : Phy_status_none); |
paul@66 | 1131 | } |
paul@66 | 1132 | |
paul@66 | 1133 | |
paul@66 | 1134 | |
paul@66 | 1135 | // Output setup operations. |
paul@66 | 1136 | |
paul@66 | 1137 | long Hdmi_jz4780_chip::enable(unsigned long pixelclock) |
paul@66 | 1138 | { |
paul@66 | 1139 | _pixelclock = pixelclock; |
paul@66 | 1140 | |
paul@66 | 1141 | // Disable frame composer overflow interrupts. |
paul@66 | 1142 | |
paul@66 | 1143 | enable_overflow_irq(false); |
paul@65 | 1144 | |
paul@66 | 1145 | // NOTE: Here, CEA modes are normally detected and thus the output encoding. |
paul@66 | 1146 | // NOTE: Instead, a fixed RGB output encoding and format is used. |
paul@66 | 1147 | // NOTE: Meanwhile, the input encoding and format will also be fixed to a RGB |
paul@66 | 1148 | // NOTE: representation. |
paul@66 | 1149 | |
paul@66 | 1150 | // _bits_per_channel = 8; |
paul@66 | 1151 | // _data_enable_polarity = true; |
paul@66 | 1152 | |
paul@66 | 1153 | // HDMI initialisation "step B.1": video frame initialisation. |
paul@66 | 1154 | |
paul@66 | 1155 | frame_init(); |
paul@66 | 1156 | |
paul@66 | 1157 | // HDMI initialisation "step B.2": PHY initialisation. |
paul@66 | 1158 | |
paul@66 | 1159 | long err = phy_init(); |
paul@66 | 1160 | if (err) |
paul@66 | 1161 | return err; |
paul@65 | 1162 | |
paul@66 | 1163 | // HDMI initialisation "step B.3": video signal initialisation. |
paul@66 | 1164 | |
paul@66 | 1165 | data_path_init(); |
paul@66 | 1166 | |
paul@66 | 1167 | // With audio, various clock updates are needed. |
paul@66 | 1168 | |
paul@66 | 1169 | // NOTE: DVI mode is being assumed for now, for simplicity. |
paul@66 | 1170 | |
paul@66 | 1171 | // In non-DVI mode, the AVI, vendor-specific infoframe and regular infoframe |
paul@66 | 1172 | // are set up. |
paul@66 | 1173 | |
paul@66 | 1174 | packet_init(); |
paul@66 | 1175 | csc_init(); |
paul@66 | 1176 | sample_init(); |
paul@66 | 1177 | hdcp_init(); |
paul@66 | 1178 | |
paul@66 | 1179 | // Enable frame composer overflow interrupts. |
paul@66 | 1180 | |
paul@66 | 1181 | enable_overflow_irq(true); |
paul@65 | 1182 | |
paul@65 | 1183 | return L4_EOK; |
paul@65 | 1184 | } |
paul@65 | 1185 | |
paul@66 | 1186 | void Hdmi_jz4780_chip::enable_overflow_irq(bool enable) |
paul@66 | 1187 | { |
paul@71 | 1188 | if (!enable) |
paul@71 | 1189 | reg_update(Fc_int_mask2, Fc_int_status2_overflow, !enable); |
paul@71 | 1190 | |
paul@71 | 1191 | // Apparent workaround required. |
paul@71 | 1192 | |
paul@71 | 1193 | else |
paul@71 | 1194 | { |
paul@71 | 1195 | uint8_t config = _regs[Fc_video_config]; |
paul@71 | 1196 | |
paul@71 | 1197 | _regs[Main_software_reset] = ~(Main_software_reset_tmds); |
paul@71 | 1198 | |
paul@71 | 1199 | for (int i = 0; i < 4; i++) |
paul@71 | 1200 | _regs[Fc_video_config] = config; |
paul@71 | 1201 | } |
paul@66 | 1202 | } |
paul@66 | 1203 | |
paul@66 | 1204 | void Hdmi_jz4780_chip::frame_init() |
paul@66 | 1205 | { |
paul@66 | 1206 | // Initialise the video configuration. This is rather like the initialisation |
paul@66 | 1207 | // of the LCD controller. The sync and data enable polarities are set up, plus |
paul@66 | 1208 | // extras like HDCP, DVI mode, progressive/interlace. |
paul@66 | 1209 | // NOTE: Here, the JZ4740-specific configuration is used to store the picture |
paul@66 | 1210 | // NOTE: properties, but a neutral structure should be adopted. |
paul@66 | 1211 | |
paul@66 | 1212 | uint8_t config = 0; |
paul@66 | 1213 | |
paul@66 | 1214 | config |= (_panel->config & Jz4740_lcd_hsync_negative) |
paul@66 | 1215 | ? Fc_video_config_hsync_active_low |
paul@66 | 1216 | : Fc_video_config_hsync_active_high; |
paul@66 | 1217 | |
paul@66 | 1218 | config |= (_panel->config & Jz4740_lcd_vsync_negative) |
paul@66 | 1219 | ? Fc_video_config_vsync_active_low |
paul@66 | 1220 | : Fc_video_config_vsync_active_high; |
paul@66 | 1221 | |
paul@66 | 1222 | config |= (_panel->config & Jz4740_lcd_de_negative) |
paul@66 | 1223 | ? Fc_video_config_data_enable_active_low |
paul@66 | 1224 | : Fc_video_config_data_enable_active_high; |
paul@66 | 1225 | |
paul@66 | 1226 | // NOTE: Only supporting DVI mode so far. |
paul@66 | 1227 | |
paul@66 | 1228 | config |= Fc_video_config_dvi_mode; |
paul@66 | 1229 | |
paul@66 | 1230 | // NOTE: Not supporting HDCP. |
paul@66 | 1231 | |
paul@66 | 1232 | config |= Fc_video_config_hdcp_keepout_inactive; |
paul@66 | 1233 | |
paul@66 | 1234 | // NOTE: Only supporting progressive scan so far. |
paul@66 | 1235 | |
paul@66 | 1236 | config |= Fc_video_config_progressive; |
paul@66 | 1237 | config |= Fc_video_config_osc_active_low; |
paul@66 | 1238 | |
paul@66 | 1239 | _regs[Fc_video_config] = config; |
paul@66 | 1240 | |
paul@66 | 1241 | // Then, the frame characteristics (visible area, sync pulse) are set. Indeed, |
paul@66 | 1242 | // the frame area details should be practically the same as those used by the |
paul@66 | 1243 | // LCD controller. |
paul@66 | 1244 | |
paul@66 | 1245 | uint16_t hblank = _panel->line_start + _panel->line_end + _panel->hsync, |
paul@66 | 1246 | vblank = _panel->frame_start + _panel->frame_end + _panel->vsync, |
paul@66 | 1247 | hsync_delay = _panel->line_end, |
paul@66 | 1248 | vsync_delay = _panel->frame_end, |
paul@66 | 1249 | hsync_width = _panel->hsync, |
paul@66 | 1250 | vsync_height = _panel->vsync; |
paul@66 | 1251 | |
paul@66 | 1252 | _regs[Fc_horizontal_active_width1] = (_panel->width >> 8) & 0xff; |
paul@66 | 1253 | _regs[Fc_horizontal_active_width0] = _panel->width & 0xff; |
paul@66 | 1254 | |
paul@66 | 1255 | _regs[Fc_horizontal_blank_width1] = (hblank >> 8) & 0xff; |
paul@66 | 1256 | _regs[Fc_horizontal_blank_width0] = hblank & 0xff; |
paul@66 | 1257 | |
paul@66 | 1258 | _regs[Fc_vertical_active_height1] = (_panel->height >> 8) & 0xff; |
paul@66 | 1259 | _regs[Fc_vertical_active_height0] = _panel->height & 0xff; |
paul@66 | 1260 | |
paul@66 | 1261 | _regs[Fc_vertical_blank_height] = vblank & 0xff; |
paul@66 | 1262 | |
paul@66 | 1263 | _regs[Fc_hsync_delay1] = (hsync_delay >> 8) & 0xff; |
paul@66 | 1264 | _regs[Fc_hsync_delay0] = hsync_delay & 0xff; |
paul@66 | 1265 | |
paul@66 | 1266 | _regs[Fc_vsync_delay] = vsync_delay & 0xff; |
paul@66 | 1267 | |
paul@66 | 1268 | _regs[Fc_hsync_width1] = (hsync_width >> 8) & 0xff; |
paul@66 | 1269 | _regs[Fc_hsync_width0] = hsync_width & 0xff; |
paul@66 | 1270 | |
paul@66 | 1271 | _regs[Fc_vsync_height] = vsync_height & 0xff; |
paul@66 | 1272 | } |
paul@66 | 1273 | |
paul@66 | 1274 | void Hdmi_jz4780_chip::data_path_init() |
paul@66 | 1275 | { |
paul@66 | 1276 | // Initialise the path of the video data. Here, the elements of the data |
paul@66 | 1277 | // stream are defined such as the control period duration, data channel |
paul@66 | 1278 | // characteristics, pixel and TMDS clocks, and the involvement of colour space |
paul@66 | 1279 | // conversion. |
paul@66 | 1280 | |
paul@66 | 1281 | // Control period minimum duration. |
paul@66 | 1282 | |
paul@66 | 1283 | _regs[Fc_control_duration] = 12; |
paul@66 | 1284 | _regs[Fc_ex_control_duration] = 32; |
paul@66 | 1285 | _regs[Fc_ex_control_space] = 1; |
paul@66 | 1286 | |
paul@66 | 1287 | // Set to fill TMDS data channels. |
paul@66 | 1288 | |
paul@66 | 1289 | _regs[Fc_channel0_preamble] = 0x0b; |
paul@66 | 1290 | _regs[Fc_channel1_preamble] = 0x16; |
paul@66 | 1291 | _regs[Fc_channel2_preamble] = 0x21; |
paul@66 | 1292 | |
paul@66 | 1293 | // Apparent two-stage clock activation. |
paul@66 | 1294 | |
paul@66 | 1295 | uint8_t clock_disable = Main_clock_disable_hdcp | |
paul@66 | 1296 | Main_clock_disable_csc | |
paul@66 | 1297 | Main_clock_disable_audio | |
paul@66 | 1298 | Main_clock_disable_prep | |
paul@66 | 1299 | Main_clock_disable_tmds; |
paul@66 | 1300 | |
paul@66 | 1301 | // Activate the pixel clock. |
paul@66 | 1302 | |
paul@66 | 1303 | _regs[Main_clock_disable] = clock_disable; |
paul@66 | 1304 | |
paul@66 | 1305 | // Then activate the TMDS clock. |
paul@66 | 1306 | |
paul@66 | 1307 | clock_disable &= ~(Main_clock_disable_tmds); |
paul@66 | 1308 | _regs[Main_clock_disable] = clock_disable; |
paul@66 | 1309 | |
paul@66 | 1310 | // NOTE: Bypass colour space conversion for now. |
paul@66 | 1311 | |
paul@66 | 1312 | _regs[Main_flow_control] = Main_flow_control_csc_inactive; |
paul@66 | 1313 | } |
paul@66 | 1314 | |
paul@66 | 1315 | void Hdmi_jz4780_chip::packet_init() |
paul@66 | 1316 | { |
paul@66 | 1317 | // Initialise the video packet details. |
paul@66 | 1318 | // NOTE: With 24bpp RGB output only for now, no pixel repetition. |
paul@66 | 1319 | |
paul@66 | 1320 | int colour_depth = 4; |
paul@66 | 1321 | |
paul@71 | 1322 | _regs[Packet_pr_cd] = |
paul@71 | 1323 | ((colour_depth << Packet_pr_cd_depth_offset) & |
paul@71 | 1324 | Packet_pr_cd_depth_mask); |
paul@66 | 1325 | |
paul@66 | 1326 | _regs[Packet_remap] = Packet_remap_ycc422_16bit; |
paul@66 | 1327 | |
paul@66 | 1328 | reg_fill_field(Packet_stuffing, Packet_stuffing_pr | |
paul@66 | 1329 | Packet_stuffing_default_phase | |
paul@66 | 1330 | Packet_stuffing_pp | |
paul@66 | 1331 | Packet_stuffing_ycc422); |
paul@66 | 1332 | |
paul@66 | 1333 | // Disable pixel repeater. |
paul@66 | 1334 | |
paul@71 | 1335 | reg_update_field(Packet_config, Packet_config_bypass_enable | |
paul@71 | 1336 | Packet_config_pr_enable | |
paul@66 | 1337 | Packet_config_pp_enable | |
paul@66 | 1338 | Packet_config_ycc422_enable | |
paul@66 | 1339 | Packet_config_bypass_select_packetizer | |
paul@71 | 1340 | Packet_config_output_selector_mask, |
paul@66 | 1341 | Packet_config_bypass_enable | |
paul@71 | 1342 | Packet_config_bypass_select_packetizer | |
paul@66 | 1343 | Packet_config_output_selector_bypass); |
paul@66 | 1344 | } |
paul@66 | 1345 | |
paul@66 | 1346 | void Hdmi_jz4780_chip::csc_init() |
paul@66 | 1347 | { |
paul@66 | 1348 | // Initialise the colour space conversion details. |
paul@66 | 1349 | // NOTE: No conversion will be done yet (see data_path_init). |
paul@66 | 1350 | |
paul@66 | 1351 | _regs[Csc_config] = Csc_config_interpolation_disable | |
paul@66 | 1352 | Csc_config_decimation_disable; |
paul@66 | 1353 | |
paul@66 | 1354 | // NOTE: Use 8bpc (24bpp) for now. |
paul@66 | 1355 | |
paul@66 | 1356 | reg_update_field(Csc_scale, Csc_scale_colour_depth_mask, Csc_scale_colour_depth_24bpp); |
paul@66 | 1357 | |
paul@66 | 1358 | // NOTE: Coefficients should be set here. |
paul@66 | 1359 | } |
paul@66 | 1360 | |
paul@66 | 1361 | void Hdmi_jz4780_chip::sample_init() |
paul@66 | 1362 | { |
paul@66 | 1363 | // Initialise the mapping of video input data. |
paul@66 | 1364 | // NOTE: With 24bpp RGB input only for now. |
paul@66 | 1365 | |
paul@66 | 1366 | int colour_format = 0x01; |
paul@66 | 1367 | |
paul@66 | 1368 | // Data enable inactive. |
paul@66 | 1369 | |
paul@66 | 1370 | _regs[Sample_video_config] = (colour_format & Sample_video_config_mapping_mask); |
paul@66 | 1371 | |
paul@66 | 1372 | // Transmission stuffing when data enable is inactive. |
paul@66 | 1373 | |
paul@66 | 1374 | _regs[Sample_video_stuffing] = Sample_video_stuffing_bdb_data | |
paul@66 | 1375 | Sample_video_stuffing_rcr_data | |
paul@66 | 1376 | Sample_video_stuffing_gy_data; |
paul@66 | 1377 | |
paul@66 | 1378 | _regs[Sample_gy_data0] = 0; |
paul@66 | 1379 | _regs[Sample_gy_data1] = 0; |
paul@66 | 1380 | _regs[Sample_rcr_data0] = 0; |
paul@66 | 1381 | _regs[Sample_rcr_data1] = 0; |
paul@66 | 1382 | _regs[Sample_bcb_data0] = 0; |
paul@66 | 1383 | _regs[Sample_bcb_data1] = 0; |
paul@66 | 1384 | } |
paul@66 | 1385 | |
paul@66 | 1386 | void Hdmi_jz4780_chip::hdcp_init() |
paul@66 | 1387 | { |
paul@66 | 1388 | // Initialise HDCP registers, mostly turning things off. |
paul@66 | 1389 | |
paul@66 | 1390 | reg_update(Hdcp_config0, Hdcp_config0_rxdetect_enable, false); |
paul@66 | 1391 | |
paul@66 | 1392 | reg_update(Hdcp_video_polarity, |
paul@66 | 1393 | Hdcp_video_polarity_data_enable_active_high, |
paul@66 | 1394 | !(_panel->config & Jz4740_lcd_de_negative)); |
paul@66 | 1395 | |
paul@66 | 1396 | reg_update(Hdcp_config1, Hdcp_config1_encryption_disable, true); |
paul@66 | 1397 | } |
paul@66 | 1398 | |
paul@62 | 1399 | |
paul@62 | 1400 | |
paul@62 | 1401 | // C language interface functions. |
paul@62 | 1402 | |
paul@66 | 1403 | void *jz4780_hdmi_init(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq, |
paul@66 | 1404 | struct Jz4740_lcd_panel *panel) |
paul@62 | 1405 | { |
paul@66 | 1406 | return (void *) new Hdmi_jz4780_chip(start, end, irq, panel); |
paul@62 | 1407 | } |
paul@62 | 1408 | |
paul@62 | 1409 | void jz4780_hdmi_get_version(void *hdmi, uint8_t *major, uint16_t *minor) |
paul@62 | 1410 | { |
paul@62 | 1411 | static_cast<Hdmi_jz4780_chip *>(hdmi)->get_version(major, minor); |
paul@62 | 1412 | } |
paul@62 | 1413 | |
paul@66 | 1414 | void jz4780_hdmi_get_phy_capabilities(void *hdmi, const struct Phy_capabilities **phy_def) |
paul@66 | 1415 | { |
paul@66 | 1416 | static_cast<Hdmi_jz4780_chip *>(hdmi)->get_phy_capabilities(phy_def); |
paul@66 | 1417 | } |
paul@66 | 1418 | |
paul@62 | 1419 | int jz4780_hdmi_i2c_read(void *hdmi, uint8_t *buf, unsigned int length) |
paul@62 | 1420 | { |
paul@62 | 1421 | return static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_read(buf, length); |
paul@62 | 1422 | } |
paul@62 | 1423 | |
paul@62 | 1424 | void jz4780_hdmi_i2c_set_address(void *hdmi, uint8_t address) |
paul@62 | 1425 | { |
paul@62 | 1426 | static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_address(address); |
paul@62 | 1427 | } |
paul@62 | 1428 | |
paul@62 | 1429 | void jz4780_hdmi_i2c_set_segment(void *hdmi, uint8_t segment) |
paul@62 | 1430 | { |
paul@62 | 1431 | static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_segment(segment); |
paul@62 | 1432 | } |
paul@62 | 1433 | |
paul@62 | 1434 | void jz4780_hdmi_i2c_set_register(void *hdmi, uint8_t device_register) |
paul@62 | 1435 | { |
paul@62 | 1436 | static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_register(device_register); |
paul@62 | 1437 | } |
paul@65 | 1438 | |
paul@65 | 1439 | int jz4780_hdmi_connected(void *hdmi) |
paul@65 | 1440 | { |
paul@65 | 1441 | return (int) static_cast<Hdmi_jz4780_chip *>(hdmi)->connected(); |
paul@65 | 1442 | } |
paul@65 | 1443 | |
paul@65 | 1444 | long jz4780_hdmi_wait_for_connection(void *hdmi) |
paul@65 | 1445 | { |
paul@65 | 1446 | return static_cast<Hdmi_jz4780_chip *>(hdmi)->wait_for_connection(); |
paul@65 | 1447 | } |
paul@66 | 1448 | |
paul@66 | 1449 | long jz4780_hdmi_enable(void *hdmi, unsigned long pixelclock) |
paul@66 | 1450 | { |
paul@66 | 1451 | return static_cast<Hdmi_jz4780_chip *>(hdmi)->enable(pixelclock); |
paul@66 | 1452 | } |