paul@123 | 1 | /* |
paul@123 | 2 | * DMA support for the JZ4730. |
paul@123 | 3 | * |
paul@268 | 4 | * Copyright (C) 2021, 2024 Paul Boddie <paul@boddie.org.uk> |
paul@123 | 5 | * |
paul@123 | 6 | * This program is free software; you can redistribute it and/or |
paul@123 | 7 | * modify it under the terms of the GNU General Public License as |
paul@123 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@123 | 9 | * the License, or (at your option) any later version. |
paul@123 | 10 | * |
paul@123 | 11 | * This program is distributed in the hope that it will be useful, |
paul@123 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@123 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@123 | 14 | * GNU General Public License for more details. |
paul@123 | 15 | * |
paul@123 | 16 | * You should have received a copy of the GNU General Public License |
paul@123 | 17 | * along with this program; if not, write to the Free Software |
paul@123 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@123 | 19 | * Boston, MA 02110-1301, USA |
paul@123 | 20 | */ |
paul@123 | 21 | |
paul@123 | 22 | #include <l4/devices/dma-jz4730.h> |
paul@123 | 23 | #include <l4/devices/hw_mmio_register_block.h> |
paul@123 | 24 | |
paul@123 | 25 | #include <l4/sys/ipc.h> |
paul@123 | 26 | #include <l4/sys/irq.h> |
paul@268 | 27 | #include <l4/sys/rcv_endpoint.h> |
paul@123 | 28 | #include <l4/util/util.h> |
paul@123 | 29 | |
paul@268 | 30 | #include <pthread.h> |
paul@268 | 31 | #include <pthread-l4.h> |
paul@268 | 32 | |
paul@204 | 33 | #include <stdio.h> |
paul@204 | 34 | |
paul@204 | 35 | |
paul@123 | 36 | |
paul@123 | 37 | enum Global_regs |
paul@123 | 38 | { |
paul@123 | 39 | Dma_irq_pending = 0xf8, // IRQP |
paul@123 | 40 | Dma_control = 0xfc, // DMAC |
paul@123 | 41 | }; |
paul@123 | 42 | |
paul@123 | 43 | enum Channel_regs |
paul@123 | 44 | { |
paul@123 | 45 | Dma_source = 0x00, // DSA |
paul@123 | 46 | Dma_destination = 0x04, // DDA |
paul@123 | 47 | Dma_transfer_count = 0x08, // DTC |
paul@123 | 48 | Dma_request_source = 0x0c, // DRT |
paul@123 | 49 | Dma_control_status = 0x10, // DCS |
paul@123 | 50 | }; |
paul@123 | 51 | |
paul@123 | 52 | enum Dma_irq_pending_shifts : unsigned |
paul@123 | 53 | { |
paul@123 | 54 | Dma_irq_pending_ch0 = 15, |
paul@123 | 55 | Dma_irq_pending_ch1 = 14, |
paul@123 | 56 | Dma_irq_pending_ch2 = 13, |
paul@123 | 57 | Dma_irq_pending_ch3 = 12, |
paul@123 | 58 | Dma_irq_pending_ch4 = 11, |
paul@123 | 59 | Dma_irq_pending_ch5 = 10, |
paul@123 | 60 | }; |
paul@123 | 61 | |
paul@123 | 62 | enum Dma_control_bits : unsigned |
paul@123 | 63 | { |
paul@123 | 64 | Dma_control_priority_mode = 0x100, // PM |
paul@123 | 65 | Dma_control_halt_occurred = 0x008, // HLT |
paul@123 | 66 | Dma_control_address_error = 0x004, // AR |
paul@123 | 67 | Dma_control_enable = 0x001, // DMAE |
paul@123 | 68 | }; |
paul@123 | 69 | |
paul@123 | 70 | enum Dma_control_priority_modes : unsigned |
paul@123 | 71 | { |
paul@123 | 72 | Dma_priority_mode_01234567 = 0, |
paul@123 | 73 | Dma_priority_mode_02314675 = 1, |
paul@123 | 74 | Dma_priority_mode_20136457 = 2, |
paul@123 | 75 | Dma_priority_mode_round_robin = 3, |
paul@123 | 76 | }; |
paul@123 | 77 | |
paul@123 | 78 | enum Dma_transfer_count_bits : unsigned |
paul@123 | 79 | { |
paul@123 | 80 | Dma_transfer_count_mask = 0x00ffffff, |
paul@123 | 81 | }; |
paul@123 | 82 | |
paul@123 | 83 | enum Dma_request_source_bits : unsigned |
paul@123 | 84 | { |
paul@123 | 85 | Dma_request_type_mask = 0x0000001f, |
paul@123 | 86 | }; |
paul@123 | 87 | |
paul@123 | 88 | enum Dma_control_status_shifts : unsigned |
paul@123 | 89 | { |
paul@123 | 90 | Dma_ext_output_polarity = 31, |
paul@123 | 91 | Dma_ext_output_mode_cycle = 30, |
paul@123 | 92 | Dma_ext_req_detect_mode = 28, |
paul@123 | 93 | Dma_ext_end_of_process_mode = 27, |
paul@123 | 94 | Dma_req_detect_int_length = 16, |
paul@123 | 95 | Dma_source_port_width = 14, |
paul@123 | 96 | Dma_dest_port_width = 12, |
paul@123 | 97 | Dma_trans_unit_size = 8, |
paul@123 | 98 | Dma_trans_mode = 7, |
paul@123 | 99 | }; |
paul@123 | 100 | |
paul@123 | 101 | enum Dma_control_status_bits : unsigned |
paul@123 | 102 | { |
paul@123 | 103 | Dma_source_address_incr = 0x00800000, |
paul@204 | 104 | Dma_source_address_no_incr = 0x00000000, |
paul@123 | 105 | Dma_dest_address_incr = 0x00400000, |
paul@204 | 106 | Dma_dest_address_no_incr = 0x00000000, |
paul@204 | 107 | |
paul@204 | 108 | Dma_trans_unit_size_32_bit = 0x00000000, |
paul@204 | 109 | Dma_trans_unit_size_8_bit = 0x00000100, |
paul@204 | 110 | Dma_trans_unit_size_16_bit = 0x00000200, |
paul@204 | 111 | Dma_trans_unit_size_16_byte = 0x00000300, |
paul@204 | 112 | Dma_trans_unit_size_32_byte = 0x00000400, |
paul@204 | 113 | |
paul@123 | 114 | Dma_address_error = 0x00000010, |
paul@123 | 115 | Dma_trans_completed = 0x00000008, |
paul@123 | 116 | Dma_trans_halted = 0x00000004, |
paul@123 | 117 | Dma_channel_irq_enable = 0x00000002, |
paul@123 | 118 | Dma_channel_enable = 0x00000001, |
paul@123 | 119 | }; |
paul@123 | 120 | |
paul@123 | 121 | enum Dma_port_width_values : unsigned |
paul@123 | 122 | { |
paul@123 | 123 | Dma_port_width_32_bit = 0, |
paul@123 | 124 | Dma_port_width_8_bit = 1, |
paul@123 | 125 | Dma_port_width_16_bit = 2, |
paul@123 | 126 | }; |
paul@123 | 127 | |
paul@123 | 128 | enum Dma_trans_mode_values : unsigned |
paul@123 | 129 | { |
paul@123 | 130 | Dma_trans_mode_single = 0, |
paul@123 | 131 | Dma_trans_mode_block = 1, |
paul@123 | 132 | }; |
paul@123 | 133 | |
paul@123 | 134 | |
paul@123 | 135 | |
paul@123 | 136 | // Initialise a channel. |
paul@123 | 137 | |
paul@123 | 138 | Dma_jz4730_channel::Dma_jz4730_channel(Dma_jz4730_chip *chip, uint8_t channel, |
paul@123 | 139 | l4_addr_t start, l4_cap_idx_t irq) |
paul@123 | 140 | : _chip(chip), _channel(channel), _irq(irq) |
paul@123 | 141 | { |
paul@123 | 142 | _regs = new Hw::Mmio_register_block<32>(start); |
paul@123 | 143 | } |
paul@123 | 144 | |
paul@123 | 145 | // Encode flags for an external transfer. |
paul@123 | 146 | |
paul@123 | 147 | uint32_t |
paul@123 | 148 | Dma_jz4730_channel::encode_external_transfer(enum Dma_jz4730_request_type type) |
paul@123 | 149 | { |
paul@123 | 150 | int external = (type == Dma_request_external) ? 1 : 0; |
paul@123 | 151 | |
paul@123 | 152 | return |
paul@123 | 153 | ((external ? (int) _ext_output_polarity : 0) << Dma_ext_output_polarity) | |
paul@123 | 154 | ((external ? (int) _ext_output_mode_cycle : 0) << Dma_ext_output_mode_cycle) | |
paul@123 | 155 | ((external ? (int) _ext_req_detect_mode : 0) << Dma_ext_req_detect_mode) | |
paul@123 | 156 | ((external ? (int) _ext_end_of_process_mode : 0) << Dma_ext_end_of_process_mode); |
paul@123 | 157 | } |
paul@123 | 158 | |
paul@123 | 159 | // Return the closest interval length greater than or equal to the number of |
paul@123 | 160 | // units given encoded in the request detection interval length field of the |
paul@123 | 161 | // control/status register. |
paul@123 | 162 | |
paul@123 | 163 | uint32_t |
paul@123 | 164 | Dma_jz4730_channel::encode_req_detect_int_length(uint8_t units) |
paul@123 | 165 | { |
paul@123 | 166 | static uint8_t lengths[] = {0, 2, 4, 8, 12, 16, 20, 24, 28, 32, 48, 60, 64, 124, 128, 200}; |
paul@123 | 167 | int i; |
paul@123 | 168 | |
paul@123 | 169 | if (!units) |
paul@123 | 170 | return 0; |
paul@123 | 171 | |
paul@204 | 172 | for (i = 0; i <= 15; i++) |
paul@123 | 173 | { |
paul@204 | 174 | if (lengths[i] >= units) |
paul@123 | 175 | break; |
paul@123 | 176 | } |
paul@123 | 177 | |
paul@204 | 178 | return i << Dma_req_detect_int_length; |
paul@123 | 179 | } |
paul@123 | 180 | |
paul@204 | 181 | // Encode the appropriate source port width. |
paul@123 | 182 | |
paul@123 | 183 | uint32_t |
paul@204 | 184 | Dma_jz4730_channel::encode_source_port_width(uint8_t width) |
paul@123 | 185 | { |
paul@204 | 186 | switch (width) |
paul@123 | 187 | { |
paul@204 | 188 | case 1: |
paul@123 | 189 | return Dma_port_width_8_bit << Dma_source_port_width; |
paul@123 | 190 | |
paul@123 | 191 | default: |
paul@123 | 192 | return Dma_port_width_32_bit << Dma_source_port_width; |
paul@123 | 193 | } |
paul@123 | 194 | } |
paul@123 | 195 | |
paul@123 | 196 | // Encode the appropriate destination port width for the given request type. |
paul@123 | 197 | |
paul@123 | 198 | uint32_t |
paul@204 | 199 | Dma_jz4730_channel::encode_destination_port_width(uint8_t width) |
paul@123 | 200 | { |
paul@204 | 201 | switch (width) |
paul@123 | 202 | { |
paul@204 | 203 | case 1: |
paul@123 | 204 | return Dma_port_width_8_bit << Dma_dest_port_width; |
paul@123 | 205 | |
paul@123 | 206 | default: |
paul@123 | 207 | return Dma_port_width_32_bit << Dma_dest_port_width; |
paul@123 | 208 | } |
paul@123 | 209 | } |
paul@123 | 210 | |
paul@204 | 211 | // Encode the transfer unit size. |
paul@204 | 212 | |
paul@204 | 213 | uint32_t |
paul@204 | 214 | Dma_jz4730_channel::encode_transfer_unit_size(uint8_t size) |
paul@204 | 215 | { |
paul@204 | 216 | switch (size) |
paul@204 | 217 | { |
paul@204 | 218 | case 1: |
paul@204 | 219 | return Dma_trans_unit_size_8_bit; |
paul@204 | 220 | |
paul@204 | 221 | case 2: |
paul@204 | 222 | return Dma_trans_unit_size_16_bit; |
paul@204 | 223 | |
paul@204 | 224 | case 16: |
paul@204 | 225 | return Dma_trans_unit_size_16_byte; |
paul@204 | 226 | |
paul@204 | 227 | case 32: |
paul@204 | 228 | return Dma_trans_unit_size_32_byte; |
paul@204 | 229 | |
paul@204 | 230 | default: |
paul@204 | 231 | return Dma_trans_unit_size_32_bit; |
paul@204 | 232 | } |
paul@204 | 233 | } |
paul@204 | 234 | |
paul@123 | 235 | // Transfer data between memory locations. |
paul@123 | 236 | |
paul@123 | 237 | unsigned int |
paul@123 | 238 | Dma_jz4730_channel::transfer(uint32_t source, uint32_t destination, |
paul@123 | 239 | unsigned int count, |
paul@204 | 240 | bool source_increment, bool destination_increment, |
paul@204 | 241 | uint8_t source_width, uint8_t destination_width, |
paul@204 | 242 | uint8_t transfer_unit_size, |
paul@123 | 243 | enum Dma_jz4730_request_type type) |
paul@123 | 244 | { |
paul@123 | 245 | // Ensure an absence of address error and halt conditions globally and in this channel. |
paul@123 | 246 | |
paul@123 | 247 | if (error() || halted()) |
paul@123 | 248 | return 0; |
paul@123 | 249 | |
paul@123 | 250 | // Ensure an absence of transaction completed and zero transfer count for this channel. |
paul@123 | 251 | |
paul@123 | 252 | if (completed() || _regs[Dma_transfer_count]) |
paul@123 | 253 | return 0; |
paul@123 | 254 | |
paul@123 | 255 | // Disable the channel. |
paul@123 | 256 | |
paul@123 | 257 | _regs[Dma_control_status] = _regs[Dma_control_status] & ~Dma_channel_enable; |
paul@123 | 258 | |
paul@123 | 259 | // Set addresses. |
paul@123 | 260 | |
paul@123 | 261 | _regs[Dma_source] = source; |
paul@123 | 262 | _regs[Dma_destination] = destination; |
paul@123 | 263 | |
paul@123 | 264 | // Set transfer count to the number of units. |
paul@123 | 265 | |
paul@204 | 266 | unsigned int units = count < Dma_transfer_count_mask ? count : Dma_transfer_count_mask; |
paul@204 | 267 | |
paul@204 | 268 | _regs[Dma_transfer_count] = units; |
paul@123 | 269 | |
paul@123 | 270 | // Set auto-request for memory-to-memory transfers. Otherwise, set the |
paul@123 | 271 | // indicated request type. |
paul@123 | 272 | |
paul@123 | 273 | _regs[Dma_request_source] = type; |
paul@123 | 274 | |
paul@123 | 275 | // Set control/status fields. |
paul@123 | 276 | // Enable the channel (and peripheral). |
paul@123 | 277 | |
paul@123 | 278 | /* NOTE: To be considered... |
paul@123 | 279 | * request detection interval length (currently left as 0) |
paul@123 | 280 | * increments and port widths for external transfers |
paul@123 | 281 | * port width overriding (for AIC...) |
paul@123 | 282 | * transfer mode (currently left as single) |
paul@123 | 283 | */ |
paul@123 | 284 | |
paul@123 | 285 | _regs[Dma_control_status] = encode_external_transfer(type) | |
paul@204 | 286 | (source_increment ? Dma_source_address_incr : Dma_source_address_no_incr) | |
paul@204 | 287 | (destination_increment ? Dma_dest_address_incr : Dma_dest_address_no_incr) | |
paul@204 | 288 | encode_source_port_width(source_width) | |
paul@204 | 289 | encode_destination_port_width(destination_width) | |
paul@204 | 290 | encode_transfer_unit_size(transfer_unit_size) | |
paul@123 | 291 | (Dma_trans_mode_single << Dma_trans_mode) | |
paul@123 | 292 | Dma_channel_irq_enable | |
paul@123 | 293 | Dma_channel_enable; |
paul@123 | 294 | |
paul@204 | 295 | // Return the number of units to transfer. |
paul@204 | 296 | |
paul@204 | 297 | return units; |
paul@204 | 298 | } |
paul@204 | 299 | |
paul@204 | 300 | unsigned int |
paul@204 | 301 | Dma_jz4730_channel::wait() |
paul@204 | 302 | { |
paul@123 | 303 | // An interrupt will occur upon completion, the completion flag will be set |
paul@123 | 304 | // and the transfer count will be zero. |
paul@123 | 305 | |
paul@204 | 306 | unsigned int remaining = 0; |
paul@123 | 307 | |
paul@123 | 308 | do |
paul@123 | 309 | { |
paul@123 | 310 | if (!wait_for_irq(1000000)) |
paul@123 | 311 | printf("status = %x\n", (uint32_t) _regs[Dma_control_status]); |
paul@123 | 312 | |
paul@123 | 313 | // Clearing the completion flag will clear the interrupt condition. |
paul@123 | 314 | // Any remaining units must be read before clearing the condition. |
paul@123 | 315 | |
paul@123 | 316 | else |
paul@123 | 317 | { |
paul@123 | 318 | remaining = _regs[Dma_transfer_count]; |
paul@123 | 319 | ack_irq(); |
paul@123 | 320 | break; |
paul@123 | 321 | } |
paul@123 | 322 | } |
paul@123 | 323 | while (!error() && !halted() && !completed()); |
paul@123 | 324 | |
paul@204 | 325 | // Reset the channel status. |
paul@123 | 326 | |
paul@204 | 327 | _regs[Dma_control_status] = _regs[Dma_control_status] & ~(Dma_channel_enable | |
paul@204 | 328 | Dma_trans_completed | Dma_address_error | |
paul@204 | 329 | Dma_trans_halted); |
paul@204 | 330 | _regs[Dma_transfer_count] = 0; |
paul@204 | 331 | |
paul@204 | 332 | // Return the number of remaining units. |
paul@204 | 333 | |
paul@204 | 334 | return remaining; |
paul@123 | 335 | } |
paul@123 | 336 | |
paul@123 | 337 | // Wait indefinitely for an interrupt request, returning true if one was delivered. |
paul@123 | 338 | |
paul@123 | 339 | bool |
paul@123 | 340 | Dma_jz4730_channel::wait_for_irq() |
paul@123 | 341 | { |
paul@268 | 342 | if (l4_error(l4_rcv_ep_bind_thread(_irq, pthread_l4_cap(pthread_self()), 0))) |
paul@268 | 343 | return false; |
paul@268 | 344 | |
paul@123 | 345 | return !l4_error(l4_irq_receive(_irq, L4_IPC_NEVER)) && _chip->have_interrupt(_channel); |
paul@123 | 346 | } |
paul@123 | 347 | |
paul@123 | 348 | // Wait up to the given timeout (in microseconds) for an interrupt request, |
paul@123 | 349 | // returning true if one was delivered. |
paul@123 | 350 | |
paul@123 | 351 | bool |
paul@123 | 352 | Dma_jz4730_channel::wait_for_irq(unsigned int timeout) |
paul@123 | 353 | { |
paul@268 | 354 | if (l4_error(l4_rcv_ep_bind_thread(_irq, pthread_l4_cap(pthread_self()), 0))) |
paul@268 | 355 | return false; |
paul@268 | 356 | |
paul@123 | 357 | return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, l4util_micros2l4to(timeout)))) && _chip->have_interrupt(_channel); |
paul@123 | 358 | } |
paul@123 | 359 | |
paul@123 | 360 | // Acknowledge an interrupt condition. |
paul@123 | 361 | |
paul@123 | 362 | void |
paul@123 | 363 | Dma_jz4730_channel::ack_irq() |
paul@123 | 364 | { |
paul@123 | 365 | _regs[Dma_control_status] = _regs[Dma_control_status] & ~Dma_trans_completed; |
paul@123 | 366 | } |
paul@123 | 367 | |
paul@123 | 368 | // Return whether a transfer has completed. |
paul@123 | 369 | |
paul@123 | 370 | bool |
paul@123 | 371 | Dma_jz4730_channel::completed() |
paul@123 | 372 | { |
paul@123 | 373 | return _regs[Dma_control_status] & Dma_trans_completed ? true : false; |
paul@123 | 374 | } |
paul@123 | 375 | |
paul@123 | 376 | // Return whether an address error condition has arisen. |
paul@123 | 377 | |
paul@123 | 378 | bool |
paul@123 | 379 | Dma_jz4730_channel::error() |
paul@123 | 380 | { |
paul@123 | 381 | return _regs[Dma_control_status] & Dma_address_error ? true : false; |
paul@123 | 382 | } |
paul@123 | 383 | |
paul@123 | 384 | // Return whether a transfer has halted. |
paul@123 | 385 | |
paul@123 | 386 | bool |
paul@123 | 387 | Dma_jz4730_channel::halted() |
paul@123 | 388 | { |
paul@123 | 389 | return _regs[Dma_control_status] & Dma_trans_halted ? true : false; |
paul@123 | 390 | } |
paul@123 | 391 | |
paul@123 | 392 | |
paul@123 | 393 | |
paul@123 | 394 | // Initialise the I2C controller. |
paul@123 | 395 | |
paul@123 | 396 | Dma_jz4730_chip::Dma_jz4730_chip(l4_addr_t start, l4_addr_t end, |
paul@123 | 397 | Cpm_jz4730_chip *cpm) |
paul@123 | 398 | : _start(start), _end(end), _cpm(cpm) |
paul@123 | 399 | { |
paul@123 | 400 | _regs = new Hw::Mmio_register_block<32>(start); |
paul@123 | 401 | } |
paul@123 | 402 | |
paul@123 | 403 | // Enable the peripheral. |
paul@123 | 404 | |
paul@123 | 405 | void |
paul@123 | 406 | Dma_jz4730_chip::enable() |
paul@123 | 407 | { |
paul@123 | 408 | // Make sure that the DMA clock is available. |
paul@123 | 409 | |
paul@128 | 410 | _cpm->start_clock(Clock_dma); |
paul@123 | 411 | |
paul@123 | 412 | // Enable the channel. |
paul@123 | 413 | // NOTE: No configuration is done for channel priority mode. |
paul@123 | 414 | |
paul@123 | 415 | _regs[Dma_control] = Dma_control_enable; |
paul@123 | 416 | while (!(_regs[Dma_control] & Dma_control_enable)); |
paul@123 | 417 | } |
paul@123 | 418 | |
paul@123 | 419 | // Disable the channel. |
paul@123 | 420 | |
paul@123 | 421 | void |
paul@123 | 422 | Dma_jz4730_chip::disable() |
paul@123 | 423 | { |
paul@123 | 424 | _regs[Dma_control] = 0; |
paul@123 | 425 | while (_regs[Dma_control] & Dma_control_enable); |
paul@123 | 426 | } |
paul@123 | 427 | |
paul@204 | 428 | // Obtain a channel object. |
paul@123 | 429 | |
paul@123 | 430 | Dma_jz4730_channel * |
paul@123 | 431 | Dma_jz4730_chip::get_channel(uint8_t channel, l4_cap_idx_t irq) |
paul@123 | 432 | { |
paul@123 | 433 | if (channel < 6) |
paul@123 | 434 | return new Dma_jz4730_channel(this, channel, _start + 0x20 * channel, irq); |
paul@123 | 435 | else |
paul@123 | 436 | throw -L4_EINVAL; |
paul@123 | 437 | } |
paul@123 | 438 | |
paul@123 | 439 | // Return whether an interrupt is pending on the given channel. |
paul@123 | 440 | |
paul@123 | 441 | bool |
paul@123 | 442 | Dma_jz4730_chip::have_interrupt(uint8_t channel) |
paul@123 | 443 | { |
paul@123 | 444 | return _regs[Dma_irq_pending] & (1 << (Dma_irq_pending_ch0 - channel)) ? true : false; |
paul@123 | 445 | } |
paul@123 | 446 | |
paul@123 | 447 | |
paul@123 | 448 | |
paul@123 | 449 | // C language interface functions. |
paul@123 | 450 | |
paul@123 | 451 | void *jz4730_dma_init(l4_addr_t start, l4_addr_t end, void *cpm) |
paul@123 | 452 | { |
paul@123 | 453 | return (void *) new Dma_jz4730_chip(start, end, static_cast<Cpm_jz4730_chip *>(cpm)); |
paul@123 | 454 | } |
paul@123 | 455 | |
paul@123 | 456 | void jz4730_dma_disable(void *dma_chip) |
paul@123 | 457 | { |
paul@123 | 458 | static_cast<Dma_jz4730_chip *>(dma_chip)->disable(); |
paul@123 | 459 | } |
paul@123 | 460 | |
paul@123 | 461 | void jz4730_dma_enable(void *dma_chip) |
paul@123 | 462 | { |
paul@123 | 463 | static_cast<Dma_jz4730_chip *>(dma_chip)->enable(); |
paul@123 | 464 | } |
paul@123 | 465 | |
paul@123 | 466 | void *jz4730_dma_get_channel(void *dma, uint8_t channel, l4_cap_idx_t irq) |
paul@123 | 467 | { |
paul@123 | 468 | return static_cast<Dma_jz4730_chip *>(dma)->get_channel(channel, irq); |
paul@123 | 469 | } |
paul@123 | 470 | |
paul@123 | 471 | void jz4730_dma_set_output_polarity(void *dma_channel, enum Dma_jz4730_ext_level polarity) |
paul@123 | 472 | { |
paul@123 | 473 | static_cast<Dma_jz4730_channel *>(dma_channel)->set_output_polarity(polarity); |
paul@123 | 474 | } |
paul@123 | 475 | |
paul@123 | 476 | void jz4730_dma_set_end_of_process_mode(void *dma_channel, enum Dma_jz4730_ext_level mode) |
paul@123 | 477 | { |
paul@123 | 478 | static_cast<Dma_jz4730_channel *>(dma_channel)->set_end_of_process_mode(mode); |
paul@123 | 479 | } |
paul@123 | 480 | |
paul@123 | 481 | void jz4730_dma_set_output_mode_cycle(void *dma_channel, enum Dma_jz4730_ext_output_mode_cycle cycle) |
paul@123 | 482 | { |
paul@123 | 483 | static_cast<Dma_jz4730_channel *>(dma_channel)->set_output_mode_cycle(cycle); |
paul@123 | 484 | } |
paul@123 | 485 | |
paul@123 | 486 | void jz4730_dma_set_req_detect_mode(void *dma_channel, enum Dma_jz4730_ext_req_detect_mode mode) |
paul@123 | 487 | { |
paul@123 | 488 | static_cast<Dma_jz4730_channel *>(dma_channel)->set_req_detect_mode(mode); |
paul@123 | 489 | } |
paul@123 | 490 | |
paul@204 | 491 | unsigned int jz4730_dma_transfer(void *dma_channel, |
paul@204 | 492 | uint32_t source, uint32_t destination, |
paul@204 | 493 | unsigned int count, |
paul@204 | 494 | int source_increment, int destination_increment, |
paul@204 | 495 | uint8_t source_width, uint8_t destination_width, |
paul@204 | 496 | uint8_t transfer_unit_size, |
paul@123 | 497 | enum Dma_jz4730_request_type type) |
paul@123 | 498 | { |
paul@204 | 499 | return static_cast<Dma_jz4730_channel *>(dma_channel)->transfer(source, |
paul@204 | 500 | destination, count, source_increment, destination_increment, source_width, |
paul@204 | 501 | destination_width, transfer_unit_size, type); |
paul@123 | 502 | } |
paul@204 | 503 | |
paul@204 | 504 | unsigned int jz4730_dma_wait(void *dma_channel) |
paul@204 | 505 | { |
paul@204 | 506 | return static_cast<Dma_jz4730_channel *>(dma_channel)->wait(); |
paul@204 | 507 | } |