paul@214 | 1 | /* |
paul@214 | 2 | * DMA support for the JZ4780. |
paul@214 | 3 | * NOTE: This should be combined with the X1600 support. |
paul@214 | 4 | * |
paul@214 | 5 | * Copyright (C) 2021, 2023 Paul Boddie <paul@boddie.org.uk> |
paul@214 | 6 | * |
paul@214 | 7 | * This program is free software; you can redistribute it and/or |
paul@214 | 8 | * modify it under the terms of the GNU General Public License as |
paul@214 | 9 | * published by the Free Software Foundation; either version 2 of |
paul@214 | 10 | * the License, or (at your option) any later version. |
paul@214 | 11 | * |
paul@214 | 12 | * This program is distributed in the hope that it will be useful, |
paul@214 | 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@214 | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@214 | 15 | * GNU General Public License for more details. |
paul@214 | 16 | * |
paul@214 | 17 | * You should have received a copy of the GNU General Public License |
paul@214 | 18 | * along with this program; if not, write to the Free Software |
paul@214 | 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@214 | 20 | * Boston, MA 02110-1301, USA |
paul@214 | 21 | */ |
paul@214 | 22 | |
paul@214 | 23 | #include <l4/devices/dma-jz4780.h> |
paul@214 | 24 | #include <l4/devices/hw_mmio_register_block.h> |
paul@214 | 25 | |
paul@223 | 26 | #include <l4/sys/cache.h> |
paul@214 | 27 | #include <l4/sys/ipc.h> |
paul@214 | 28 | #include <l4/sys/irq.h> |
paul@268 | 29 | #include <l4/sys/rcv_endpoint.h> |
paul@214 | 30 | #include <l4/util/util.h> |
paul@214 | 31 | |
paul@268 | 32 | #include <pthread.h> |
paul@268 | 33 | #include <pthread-l4.h> |
paul@268 | 34 | |
paul@214 | 35 | #include <stdio.h> |
paul@214 | 36 | |
paul@214 | 37 | |
paul@214 | 38 | |
paul@214 | 39 | enum Global_regs |
paul@214 | 40 | { |
paul@214 | 41 | Dma_control = 0x1000, // DMAC |
paul@214 | 42 | Dma_irq_pending = 0x1004, // DIRQP |
paul@223 | 43 | Dma_doorbell = 0x1008, // DDB |
paul@223 | 44 | Dma_doorbell_set = 0x100c, // DDS |
paul@223 | 45 | Dma_channel_programmable = 0x101c, // DMACP |
paul@223 | 46 | Dma_soft_irq_pending = 0x1020, // DSIRQP |
paul@223 | 47 | Dma_soft_irq_mask = 0x1024, // DSIRQM |
paul@223 | 48 | Dma_mcu_irq_pending = 0x1028, // DCIRQP |
paul@223 | 49 | Dma_mcu_irq_mask = 0x102c, // DCIRQM |
paul@214 | 50 | }; |
paul@214 | 51 | |
paul@214 | 52 | enum Channel_regs |
paul@214 | 53 | { |
paul@214 | 54 | Dma_source = 0x00, // DSA |
paul@214 | 55 | Dma_destination = 0x04, // DTA |
paul@214 | 56 | Dma_transfer_count = 0x08, // DTC |
paul@214 | 57 | Dma_request_source = 0x0c, // DRT |
paul@214 | 58 | Dma_control_status = 0x10, // DCS |
paul@214 | 59 | Dma_command = 0x14, // DCM |
paul@214 | 60 | Dma_descriptor_address = 0x18, // DDA |
paul@214 | 61 | Dma_stride = 0x1c, // DSD |
paul@214 | 62 | }; |
paul@214 | 63 | |
paul@214 | 64 | enum Dma_control_bits : unsigned |
paul@214 | 65 | { |
paul@214 | 66 | Dma_fast_msc_transfer = 0x80000000, // FMSC |
paul@214 | 67 | Dma_fast_ssi_transfer = 0x40000000, // FSSI |
paul@214 | 68 | Dma_fast_tssi_transfer = 0x20000000, // FTSSI |
paul@214 | 69 | Dma_fast_uart_transfer = 0x10000000, // FUART |
paul@214 | 70 | Dma_fast_aic_transfer = 0x08000000, // FAIC |
paul@214 | 71 | |
paul@214 | 72 | Dma_intc_irq_channel_mask = 0x003e0000, // INTCC |
paul@214 | 73 | Dma_intc_irq_channel_bind = 0x00010000, // INTCE |
paul@214 | 74 | |
paul@214 | 75 | Dma_control_trans_halted = 0x00000008, // HLT |
paul@214 | 76 | Dma_control_address_error = 0x00000004, // AR |
paul@214 | 77 | Dma_control_special_ch01 = 0x00000002, // CH01 |
paul@214 | 78 | Dma_control_enable = 0x00000001, // DMAE |
paul@214 | 79 | }; |
paul@214 | 80 | |
paul@214 | 81 | enum Dma_transfer_count_bits : unsigned |
paul@214 | 82 | { |
paul@223 | 83 | Dma_descriptor_offset_mask = 0xff000000, // DOA (in DES3) |
paul@214 | 84 | Dma_transfer_count_mask = 0x00ffffff, |
paul@223 | 85 | |
paul@223 | 86 | Dma_descriptor_offset_shift = 24, |
paul@214 | 87 | }; |
paul@214 | 88 | |
paul@214 | 89 | enum Dma_request_source_bits : unsigned |
paul@214 | 90 | { |
paul@214 | 91 | Dma_request_type_mask = 0x0000003f, |
paul@214 | 92 | }; |
paul@214 | 93 | |
paul@214 | 94 | enum Dma_control_status_bits : unsigned |
paul@214 | 95 | { |
paul@214 | 96 | Dma_no_descriptor_transfer = 0x80000000, |
paul@214 | 97 | Dma_8word_descriptor = 0x40000000, |
paul@223 | 98 | Dma_4word_descriptor = 0x00000000, |
paul@214 | 99 | Dma_copy_offset_mask = 0x0000ff00, |
paul@214 | 100 | Dma_address_error = 0x00000010, |
paul@214 | 101 | Dma_trans_completed = 0x00000008, |
paul@214 | 102 | Dma_trans_halted = 0x00000004, |
paul@214 | 103 | Dma_channel_enable = 0x00000001, |
paul@214 | 104 | |
paul@214 | 105 | Dma_copy_offset_shift = 8, |
paul@214 | 106 | }; |
paul@214 | 107 | |
paul@214 | 108 | enum Dma_command_bits : unsigned |
paul@214 | 109 | { |
paul@214 | 110 | Dma_special_source_mask = 0x0c000000, |
paul@214 | 111 | Dma_special_source_tcsm = 0x00000000, |
paul@214 | 112 | Dma_special_source_bch_nemc = 0x04000000, |
paul@214 | 113 | Dma_special_source_reserved_ddr = 0x08000000, |
paul@214 | 114 | |
paul@214 | 115 | Dma_special_destination_mask = 0x03000000, |
paul@214 | 116 | Dma_special_destination_tcsm = 0x00000000, |
paul@214 | 117 | Dma_special_destination_bch_nemc = 0x01000000, |
paul@214 | 118 | Dma_special_destination_reserved_ddr = 0x02000000, |
paul@214 | 119 | |
paul@214 | 120 | Dma_source_address_increment = 0x00800000, |
paul@214 | 121 | Dma_source_address_no_increment = 0x00000000, |
paul@214 | 122 | Dma_destination_address_increment = 0x00400000, |
paul@214 | 123 | Dma_destination_address_no_increment = 0x00000000, |
paul@214 | 124 | |
paul@214 | 125 | Dma_recommended_data_unit_size_mask = 0x000f0000, |
paul@214 | 126 | Dma_source_port_width_mask = 0x0000c000, |
paul@214 | 127 | Dma_destination_port_width_mask = 0x00003000, |
paul@214 | 128 | Dma_transfer_unit_size_mask = 0x00000f00, |
paul@214 | 129 | |
paul@214 | 130 | Dma_trans_unit_size_32_bit = 0x00000000, |
paul@214 | 131 | Dma_trans_unit_size_8_bit = 0x00000100, |
paul@214 | 132 | Dma_trans_unit_size_16_bit = 0x00000200, |
paul@214 | 133 | Dma_trans_unit_size_16_byte = 0x00000300, |
paul@214 | 134 | Dma_trans_unit_size_32_byte = 0x00000400, |
paul@214 | 135 | Dma_trans_unit_size_64_byte = 0x00000500, |
paul@214 | 136 | Dma_trans_unit_size_128_byte = 0x00000600, |
paul@214 | 137 | Dma_trans_unit_size_autonomous = 0x00000700, |
paul@214 | 138 | |
paul@214 | 139 | Dma_stride_enable = 0x00000004, |
paul@214 | 140 | Dma_transfer_irq_enable = 0x00000002, |
paul@214 | 141 | Dma_descriptor_link_enable = 0x00000001, |
paul@214 | 142 | |
paul@214 | 143 | Dma_recommended_data_unit_size_shift = 16, |
paul@214 | 144 | Dma_source_port_width_shift = 14, |
paul@214 | 145 | Dma_destination_port_width_shift = 12, |
paul@214 | 146 | Dma_transfer_unit_size_shift = 8, |
paul@214 | 147 | }; |
paul@214 | 148 | |
paul@214 | 149 | enum Dma_port_width_values : unsigned |
paul@214 | 150 | { |
paul@214 | 151 | Dma_port_width_32_bit = 0, |
paul@214 | 152 | Dma_port_width_8_bit = 1, |
paul@214 | 153 | Dma_port_width_16_bit = 2, |
paul@214 | 154 | }; |
paul@214 | 155 | |
paul@214 | 156 | |
paul@214 | 157 | |
paul@214 | 158 | // Initialise a channel. |
paul@214 | 159 | |
paul@214 | 160 | Dma_jz4780_channel::Dma_jz4780_channel(Dma_jz4780_chip *chip, uint8_t channel, |
paul@214 | 161 | l4_addr_t start, l4_cap_idx_t irq) |
paul@214 | 162 | : _chip(chip), _channel(channel), _irq(irq) |
paul@214 | 163 | { |
paul@214 | 164 | _regs = new Hw::Mmio_register_block<32>(start); |
paul@214 | 165 | |
paul@214 | 166 | // Initialise the transfer count. |
paul@214 | 167 | |
paul@214 | 168 | _regs[Dma_transfer_count] = 0; |
paul@214 | 169 | } |
paul@214 | 170 | |
paul@214 | 171 | // Return the closest interval length greater than or equal to the number of |
paul@214 | 172 | // units given encoded in the request detection interval length field of the |
paul@214 | 173 | // control/status register. |
paul@214 | 174 | |
paul@214 | 175 | uint32_t |
paul@214 | 176 | Dma_jz4780_channel::encode_req_detect_int_length(uint8_t units) |
paul@214 | 177 | { |
paul@214 | 178 | static uint8_t lengths[] = {0, 1, 2, 3, 4, 8, 16, 32, 64, 128}; |
paul@214 | 179 | int i; |
paul@214 | 180 | |
paul@214 | 181 | if (!units) |
paul@214 | 182 | return 0; |
paul@214 | 183 | |
paul@214 | 184 | for (i = 0; i <= 9; i++) |
paul@214 | 185 | { |
paul@214 | 186 | if (lengths[i] >= units) |
paul@214 | 187 | break; |
paul@214 | 188 | } |
paul@214 | 189 | |
paul@214 | 190 | return i << Dma_recommended_data_unit_size_shift; |
paul@214 | 191 | } |
paul@214 | 192 | |
paul@214 | 193 | // Encode the appropriate source port width for the given request type. |
paul@214 | 194 | |
paul@214 | 195 | uint32_t |
paul@214 | 196 | Dma_jz4780_channel::encode_source_port_width(uint8_t width) |
paul@214 | 197 | { |
paul@214 | 198 | switch (width) |
paul@214 | 199 | { |
paul@214 | 200 | case 1: |
paul@214 | 201 | return Dma_port_width_8_bit << Dma_source_port_width_shift; |
paul@214 | 202 | |
paul@214 | 203 | case 2: |
paul@214 | 204 | return Dma_port_width_16_bit << Dma_source_port_width_shift; |
paul@214 | 205 | |
paul@214 | 206 | default: |
paul@214 | 207 | return Dma_port_width_32_bit << Dma_source_port_width_shift; |
paul@214 | 208 | } |
paul@214 | 209 | } |
paul@214 | 210 | |
paul@214 | 211 | // Encode the appropriate destination port width for the given request type. |
paul@214 | 212 | |
paul@214 | 213 | uint32_t |
paul@214 | 214 | Dma_jz4780_channel::encode_destination_port_width(uint8_t width) |
paul@214 | 215 | { |
paul@214 | 216 | switch (width) |
paul@214 | 217 | { |
paul@214 | 218 | case 1: |
paul@214 | 219 | return Dma_port_width_8_bit << Dma_destination_port_width_shift; |
paul@214 | 220 | |
paul@214 | 221 | case 2: |
paul@214 | 222 | return Dma_port_width_16_bit << Dma_destination_port_width_shift; |
paul@214 | 223 | |
paul@214 | 224 | default: |
paul@214 | 225 | return Dma_port_width_32_bit << Dma_destination_port_width_shift; |
paul@214 | 226 | } |
paul@214 | 227 | } |
paul@214 | 228 | |
paul@214 | 229 | // Encode the transfer unit size. |
paul@214 | 230 | // NOTE: This does not handle the external case. |
paul@214 | 231 | |
paul@214 | 232 | uint32_t |
paul@214 | 233 | Dma_jz4780_channel::encode_transfer_unit_size(uint8_t size) |
paul@214 | 234 | { |
paul@214 | 235 | switch (size) |
paul@214 | 236 | { |
paul@214 | 237 | case 0: |
paul@214 | 238 | return Dma_trans_unit_size_autonomous; |
paul@214 | 239 | |
paul@214 | 240 | case 1: |
paul@214 | 241 | return Dma_trans_unit_size_8_bit; |
paul@214 | 242 | |
paul@214 | 243 | case 2: |
paul@214 | 244 | return Dma_trans_unit_size_16_bit; |
paul@214 | 245 | |
paul@214 | 246 | case 16: |
paul@214 | 247 | return Dma_trans_unit_size_16_byte; |
paul@214 | 248 | |
paul@214 | 249 | case 32: |
paul@214 | 250 | return Dma_trans_unit_size_32_byte; |
paul@214 | 251 | |
paul@214 | 252 | case 64: |
paul@214 | 253 | return Dma_trans_unit_size_64_byte; |
paul@214 | 254 | |
paul@214 | 255 | case 128: |
paul@214 | 256 | return Dma_trans_unit_size_128_byte; |
paul@214 | 257 | |
paul@214 | 258 | default: |
paul@214 | 259 | return Dma_trans_unit_size_32_bit; |
paul@214 | 260 | } |
paul@214 | 261 | } |
paul@214 | 262 | |
paul@214 | 263 | // Transfer data between memory locations. |
paul@214 | 264 | |
paul@214 | 265 | unsigned int |
paul@214 | 266 | Dma_jz4780_channel::transfer(uint32_t source, uint32_t destination, |
paul@214 | 267 | unsigned int count, |
paul@214 | 268 | bool source_increment, bool destination_increment, |
paul@214 | 269 | uint8_t source_width, uint8_t destination_width, |
paul@214 | 270 | uint8_t transfer_unit_size, |
paul@223 | 271 | enum Dma_jz4780_request_type type, |
paul@223 | 272 | l4_addr_t desc_vaddr, |
paul@223 | 273 | l4re_dma_space_dma_addr_t desc_paddr) |
paul@214 | 274 | { |
paul@214 | 275 | printf("transfer:%s%s%s%s\n", error() ? " error" : "", |
paul@214 | 276 | halted() ? " halted" : "", |
paul@214 | 277 | completed() ? " completed" : "", |
paul@214 | 278 | _regs[Dma_transfer_count] ? " count" : ""); |
paul@214 | 279 | |
paul@214 | 280 | // Ensure an absence of address error and halt conditions globally and in this channel. |
paul@214 | 281 | |
paul@214 | 282 | if (error() || halted()) |
paul@214 | 283 | return 0; |
paul@214 | 284 | |
paul@260 | 285 | // Ensure a zero transfer count for this channel. |
paul@214 | 286 | |
paul@260 | 287 | if (_regs[Dma_transfer_count]) |
paul@214 | 288 | return 0; |
paul@214 | 289 | |
paul@214 | 290 | // Disable the channel. |
paul@214 | 291 | |
paul@214 | 292 | _regs[Dma_control_status] = _regs[Dma_control_status] & ~Dma_channel_enable; |
paul@214 | 293 | |
paul@214 | 294 | // Set transfer count to the number of units. |
paul@214 | 295 | |
paul@214 | 296 | unsigned int units = count < Dma_transfer_count_mask ? count : Dma_transfer_count_mask; |
paul@214 | 297 | |
paul@223 | 298 | // NOTE: Request detection interval length (for autonomous mode) not considered. |
paul@214 | 299 | |
paul@223 | 300 | uint32_t command = (source_increment ? Dma_source_address_increment : |
paul@223 | 301 | Dma_source_address_no_increment) | |
paul@223 | 302 | (destination_increment ? Dma_destination_address_increment : |
paul@223 | 303 | Dma_destination_address_no_increment) | |
paul@223 | 304 | encode_source_port_width(source_width) | |
paul@223 | 305 | encode_destination_port_width(destination_width) | |
paul@223 | 306 | encode_transfer_unit_size(transfer_unit_size) | |
paul@223 | 307 | Dma_transfer_irq_enable; |
paul@214 | 308 | |
paul@223 | 309 | // Populate the descriptor, largely corresponding to the population of |
paul@223 | 310 | // registers when descriptors are not being used. |
paul@214 | 311 | |
paul@223 | 312 | if (desc_vaddr) |
paul@223 | 313 | { |
paul@223 | 314 | struct jz4780_dma_descriptor *desc = (struct jz4780_dma_descriptor *) desc_vaddr; |
paul@223 | 315 | |
paul@223 | 316 | // NOTE: Linking to the same descriptor. |
paul@223 | 317 | |
paul@223 | 318 | uint32_t descriptor_offset = 0; |
paul@214 | 319 | |
paul@223 | 320 | desc->command = command | Dma_descriptor_link_enable; |
paul@223 | 321 | desc->source = source; |
paul@223 | 322 | desc->destination = destination; |
paul@223 | 323 | desc->transfer_count = (units & Dma_transfer_count_mask) | |
paul@223 | 324 | (descriptor_offset << Dma_descriptor_offset_shift); |
paul@223 | 325 | desc->request_source = type; |
paul@223 | 326 | |
paul@223 | 327 | // NOTE: Stride not supported yet. |
paul@223 | 328 | |
paul@223 | 329 | l4_cache_clean_data((unsigned long) desc_vaddr, |
paul@223 | 330 | (unsigned long) desc_vaddr + sizeof(*desc)); |
paul@223 | 331 | |
paul@223 | 332 | // Commit the descriptor. |
paul@214 | 333 | |
paul@223 | 334 | _regs[Dma_descriptor_address] = desc_paddr; |
paul@223 | 335 | _chip->commit_descriptor(_channel); |
paul@223 | 336 | } |
paul@223 | 337 | |
paul@223 | 338 | // Otherwise, populate the registers for a one-off transfer. |
paul@214 | 339 | |
paul@223 | 340 | else |
paul@223 | 341 | { |
paul@223 | 342 | _regs[Dma_command] = command; |
paul@223 | 343 | _regs[Dma_source] = source; |
paul@223 | 344 | _regs[Dma_destination] = destination; |
paul@223 | 345 | _regs[Dma_transfer_count] = units & Dma_transfer_count_mask; |
paul@223 | 346 | _regs[Dma_request_source] = type; |
paul@223 | 347 | } |
paul@214 | 348 | |
paul@223 | 349 | // Enable the channel with descriptor transfer configured if appropriate. |
paul@214 | 350 | |
paul@223 | 351 | _regs[Dma_control_status] = (desc_vaddr ? Dma_8word_descriptor : |
paul@223 | 352 | Dma_no_descriptor_transfer) | |
paul@214 | 353 | Dma_channel_enable; |
paul@214 | 354 | |
paul@214 | 355 | // Return the number of units to transfer. |
paul@214 | 356 | |
paul@214 | 357 | return units; |
paul@214 | 358 | } |
paul@214 | 359 | |
paul@214 | 360 | unsigned int |
paul@214 | 361 | Dma_jz4780_channel::wait() |
paul@214 | 362 | { |
paul@214 | 363 | // An interrupt will occur upon completion, the completion flag will be set |
paul@214 | 364 | // and the transfer count will be zero. |
paul@214 | 365 | |
paul@214 | 366 | unsigned int remaining = 0; |
paul@214 | 367 | |
paul@214 | 368 | do |
paul@214 | 369 | { |
paul@214 | 370 | if (!wait_for_irq(1000000)) |
paul@214 | 371 | printf("status = %x\n", (uint32_t) _regs[Dma_control_status]); |
paul@214 | 372 | else |
paul@214 | 373 | { |
paul@214 | 374 | printf("status = %x\n", (uint32_t) _regs[Dma_control_status]); |
paul@214 | 375 | remaining = _regs[Dma_transfer_count]; |
paul@214 | 376 | ack_irq(); |
paul@214 | 377 | break; |
paul@214 | 378 | } |
paul@214 | 379 | } |
paul@214 | 380 | while (!error() && !halted() && !completed()); |
paul@214 | 381 | |
paul@214 | 382 | // Reset the channel status. |
paul@214 | 383 | |
paul@214 | 384 | _regs[Dma_control_status] = _regs[Dma_control_status] & ~(Dma_channel_enable | |
paul@214 | 385 | Dma_trans_completed | Dma_address_error | |
paul@214 | 386 | Dma_trans_halted); |
paul@214 | 387 | _regs[Dma_transfer_count] = 0; |
paul@214 | 388 | |
paul@214 | 389 | // Return the number of remaining units. |
paul@214 | 390 | |
paul@214 | 391 | return remaining; |
paul@214 | 392 | } |
paul@214 | 393 | |
paul@214 | 394 | // Wait indefinitely for an interrupt request, returning true if one was delivered. |
paul@214 | 395 | |
paul@214 | 396 | bool |
paul@214 | 397 | Dma_jz4780_channel::wait_for_irq() |
paul@214 | 398 | { |
paul@225 | 399 | if (l4_is_valid_cap(_irq)) |
paul@268 | 400 | { |
paul@268 | 401 | if (l4_error(l4_rcv_ep_bind_thread(_irq, pthread_l4_cap(pthread_self()), 0))) |
paul@268 | 402 | return false; |
paul@268 | 403 | |
paul@225 | 404 | return !l4_error(l4_irq_receive(_irq, L4_IPC_NEVER)) && _chip->have_interrupt(_channel); |
paul@268 | 405 | } |
paul@225 | 406 | else |
paul@225 | 407 | return true; |
paul@214 | 408 | } |
paul@214 | 409 | |
paul@214 | 410 | // Wait up to the given timeout (in microseconds) for an interrupt request, |
paul@214 | 411 | // returning true if one was delivered. |
paul@214 | 412 | |
paul@214 | 413 | bool |
paul@214 | 414 | Dma_jz4780_channel::wait_for_irq(unsigned int timeout) |
paul@214 | 415 | { |
paul@225 | 416 | if (l4_is_valid_cap(_irq)) |
paul@268 | 417 | { |
paul@268 | 418 | if (l4_error(l4_rcv_ep_bind_thread(_irq, pthread_l4_cap(pthread_self()), 0))) |
paul@268 | 419 | return false; |
paul@268 | 420 | |
paul@225 | 421 | return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, l4util_micros2l4to(timeout)))) && _chip->have_interrupt(_channel); |
paul@268 | 422 | } |
paul@225 | 423 | else |
paul@225 | 424 | return true; |
paul@214 | 425 | } |
paul@214 | 426 | |
paul@214 | 427 | // Acknowledge an interrupt condition. |
paul@214 | 428 | |
paul@214 | 429 | void |
paul@214 | 430 | Dma_jz4780_channel::ack_irq() |
paul@214 | 431 | { |
paul@214 | 432 | _chip->ack_irq(_channel); |
paul@214 | 433 | } |
paul@214 | 434 | |
paul@214 | 435 | // Return whether a transfer has completed. |
paul@214 | 436 | |
paul@214 | 437 | bool |
paul@214 | 438 | Dma_jz4780_channel::completed() |
paul@214 | 439 | { |
paul@214 | 440 | return _regs[Dma_control_status] & Dma_trans_completed ? true : false; |
paul@214 | 441 | } |
paul@214 | 442 | |
paul@214 | 443 | // Return whether an address error condition has arisen. |
paul@214 | 444 | |
paul@214 | 445 | bool |
paul@214 | 446 | Dma_jz4780_channel::error() |
paul@214 | 447 | { |
paul@214 | 448 | return _chip->error() || (_regs[Dma_control_status] & Dma_address_error ? true : false); |
paul@214 | 449 | } |
paul@214 | 450 | |
paul@214 | 451 | // Return whether a transfer has halted. |
paul@214 | 452 | |
paul@214 | 453 | bool |
paul@214 | 454 | Dma_jz4780_channel::halted() |
paul@214 | 455 | { |
paul@214 | 456 | return _chip->halted() || (_regs[Dma_control_status] & Dma_trans_halted ? true : false); |
paul@214 | 457 | } |
paul@214 | 458 | |
paul@214 | 459 | |
paul@214 | 460 | |
paul@214 | 461 | // Initialise the I2C controller. |
paul@214 | 462 | |
paul@214 | 463 | Dma_jz4780_chip::Dma_jz4780_chip(l4_addr_t start, l4_addr_t end, |
paul@214 | 464 | Cpm_jz4780_chip *cpm) |
paul@214 | 465 | : _start(start), _end(end), _cpm(cpm) |
paul@214 | 466 | { |
paul@214 | 467 | _regs = new Hw::Mmio_register_block<32>(start); |
paul@214 | 468 | } |
paul@214 | 469 | |
paul@214 | 470 | // Enable the peripheral. |
paul@214 | 471 | |
paul@214 | 472 | void |
paul@214 | 473 | Dma_jz4780_chip::enable() |
paul@214 | 474 | { |
paul@214 | 475 | // Make sure that the DMA clock is available. |
paul@214 | 476 | |
paul@214 | 477 | _cpm->start_clock(Clock_dma); |
paul@214 | 478 | |
paul@214 | 479 | _regs[Dma_control] = Dma_control_enable; |
paul@214 | 480 | while (!(_regs[Dma_control] & Dma_control_enable)); |
paul@214 | 481 | } |
paul@214 | 482 | |
paul@214 | 483 | // Disable the channel. |
paul@214 | 484 | |
paul@214 | 485 | void |
paul@214 | 486 | Dma_jz4780_chip::disable() |
paul@214 | 487 | { |
paul@214 | 488 | _regs[Dma_control] = 0; |
paul@214 | 489 | while (_regs[Dma_control] & Dma_control_enable); |
paul@214 | 490 | } |
paul@214 | 491 | |
paul@214 | 492 | // Obtain a channel object. |
paul@214 | 493 | |
paul@214 | 494 | Dma_jz4780_channel * |
paul@214 | 495 | Dma_jz4780_chip::get_channel(uint8_t channel, l4_cap_idx_t irq) |
paul@214 | 496 | { |
paul@214 | 497 | if (channel < 32) |
paul@214 | 498 | return new Dma_jz4780_channel(this, channel, _start + 0x20 * channel, irq); |
paul@214 | 499 | else |
paul@214 | 500 | throw -L4_EINVAL; |
paul@214 | 501 | } |
paul@214 | 502 | |
paul@214 | 503 | // Return whether an interrupt is pending on the given channel. |
paul@214 | 504 | |
paul@214 | 505 | bool |
paul@214 | 506 | Dma_jz4780_chip::have_interrupt(uint8_t channel) |
paul@214 | 507 | { |
paul@214 | 508 | return _regs[Dma_irq_pending] & (1 << channel) ? true : false; |
paul@214 | 509 | } |
paul@214 | 510 | |
paul@214 | 511 | // Acknowledge an interrupt condition on the given channel. |
paul@214 | 512 | |
paul@214 | 513 | void |
paul@214 | 514 | Dma_jz4780_chip::ack_irq(uint8_t channel) |
paul@214 | 515 | { |
paul@214 | 516 | _regs[Dma_irq_pending] = _regs[Dma_irq_pending] & ~(1 << channel); |
paul@214 | 517 | } |
paul@214 | 518 | |
paul@214 | 519 | // Return whether an address error condition has arisen. |
paul@214 | 520 | |
paul@214 | 521 | bool |
paul@214 | 522 | Dma_jz4780_chip::error() |
paul@214 | 523 | { |
paul@214 | 524 | return _regs[Dma_control] & Dma_control_address_error ? true : false; |
paul@214 | 525 | } |
paul@214 | 526 | |
paul@214 | 527 | // Return whether a transfer has halted. |
paul@214 | 528 | |
paul@214 | 529 | bool |
paul@214 | 530 | Dma_jz4780_chip::halted() |
paul@214 | 531 | { |
paul@214 | 532 | return _regs[Dma_control] & Dma_control_trans_halted ? true : false; |
paul@214 | 533 | } |
paul@214 | 534 | |
paul@223 | 535 | void |
paul@223 | 536 | Dma_jz4780_chip::commit_descriptor(uint8_t channel) |
paul@223 | 537 | { |
paul@223 | 538 | _regs[Dma_doorbell_set] = (1 << channel); |
paul@223 | 539 | } |
paul@223 | 540 | |
paul@214 | 541 | |
paul@214 | 542 | |
paul@214 | 543 | // C language interface functions. |
paul@214 | 544 | |
paul@214 | 545 | void *jz4780_dma_init(l4_addr_t start, l4_addr_t end, void *cpm) |
paul@214 | 546 | { |
paul@214 | 547 | return (void *) new Dma_jz4780_chip(start, end, static_cast<Cpm_jz4780_chip *>(cpm)); |
paul@214 | 548 | } |
paul@214 | 549 | |
paul@214 | 550 | void jz4780_dma_disable(void *dma_chip) |
paul@214 | 551 | { |
paul@214 | 552 | static_cast<Dma_jz4780_chip *>(dma_chip)->disable(); |
paul@214 | 553 | } |
paul@214 | 554 | |
paul@214 | 555 | void jz4780_dma_enable(void *dma_chip) |
paul@214 | 556 | { |
paul@214 | 557 | static_cast<Dma_jz4780_chip *>(dma_chip)->enable(); |
paul@214 | 558 | } |
paul@214 | 559 | |
paul@214 | 560 | void *jz4780_dma_get_channel(void *dma, uint8_t channel, l4_cap_idx_t irq) |
paul@214 | 561 | { |
paul@214 | 562 | return static_cast<Dma_jz4780_chip *>(dma)->get_channel(channel, irq); |
paul@214 | 563 | } |
paul@214 | 564 | |
paul@214 | 565 | unsigned int jz4780_dma_transfer(void *dma_channel, |
paul@223 | 566 | uint32_t source, uint32_t destination, |
paul@223 | 567 | unsigned int count, |
paul@223 | 568 | int source_increment, int destination_increment, |
paul@223 | 569 | uint8_t source_width, uint8_t destination_width, |
paul@223 | 570 | uint8_t transfer_unit_size, |
paul@223 | 571 | enum Dma_jz4780_request_type type) |
paul@214 | 572 | { |
paul@214 | 573 | return static_cast<Dma_jz4780_channel *>(dma_channel)->transfer(source, |
paul@214 | 574 | destination, count, source_increment, destination_increment, source_width, |
paul@214 | 575 | destination_width, transfer_unit_size, type); |
paul@214 | 576 | } |
paul@214 | 577 | |
paul@223 | 578 | unsigned int jz4780_dma_transfer_descriptor(void *dma_channel, |
paul@223 | 579 | uint32_t source, uint32_t destination, |
paul@223 | 580 | unsigned int count, |
paul@223 | 581 | int source_increment, int destination_increment, |
paul@223 | 582 | uint8_t source_width, uint8_t destination_width, |
paul@223 | 583 | uint8_t transfer_unit_size, |
paul@223 | 584 | enum Dma_jz4780_request_type type, |
paul@223 | 585 | l4_addr_t desc_vaddr, |
paul@223 | 586 | l4re_dma_space_dma_addr_t desc_paddr) |
paul@223 | 587 | { |
paul@223 | 588 | return static_cast<Dma_jz4780_channel *>(dma_channel)->transfer(source, |
paul@223 | 589 | destination, count, source_increment, destination_increment, source_width, |
paul@223 | 590 | destination_width, transfer_unit_size, type, desc_vaddr, desc_paddr); |
paul@223 | 591 | } |
paul@223 | 592 | |
paul@214 | 593 | unsigned int jz4780_dma_wait(void *dma_channel) |
paul@214 | 594 | { |
paul@214 | 595 | return static_cast<Dma_jz4780_channel *>(dma_channel)->wait(); |
paul@214 | 596 | } |