paul@204 | 1 | /* |
paul@204 | 2 | * DMA support for the X1600. |
paul@204 | 3 | * |
paul@251 | 4 | * Copyright (C) 2021, 2023, 2024 Paul Boddie <paul@boddie.org.uk> |
paul@204 | 5 | * |
paul@204 | 6 | * This program is free software; you can redistribute it and/or |
paul@204 | 7 | * modify it under the terms of the GNU General Public License as |
paul@204 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@204 | 9 | * the License, or (at your option) any later version. |
paul@204 | 10 | * |
paul@204 | 11 | * This program is distributed in the hope that it will be useful, |
paul@204 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@204 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@204 | 14 | * GNU General Public License for more details. |
paul@204 | 15 | * |
paul@204 | 16 | * You should have received a copy of the GNU General Public License |
paul@204 | 17 | * along with this program; if not, write to the Free Software |
paul@204 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@204 | 19 | * Boston, MA 02110-1301, USA |
paul@204 | 20 | */ |
paul@204 | 21 | |
paul@204 | 22 | #include <l4/devices/dma-x1600.h> |
paul@204 | 23 | #include <l4/devices/hw_mmio_register_block.h> |
paul@204 | 24 | |
paul@204 | 25 | #include <l4/sys/ipc.h> |
paul@204 | 26 | #include <l4/sys/irq.h> |
paul@268 | 27 | #include <l4/sys/rcv_endpoint.h> |
paul@204 | 28 | #include <l4/util/util.h> |
paul@204 | 29 | |
paul@268 | 30 | #include <pthread.h> |
paul@268 | 31 | #include <pthread-l4.h> |
paul@268 | 32 | |
paul@204 | 33 | #include <stdio.h> |
paul@204 | 34 | |
paul@204 | 35 | |
paul@204 | 36 | |
paul@204 | 37 | enum Global_regs |
paul@204 | 38 | { |
paul@204 | 39 | Dma_control = 0x1000, // DMAC |
paul@204 | 40 | Dma_irq_pending = 0x1004, // DIRQP |
paul@204 | 41 | }; |
paul@204 | 42 | |
paul@204 | 43 | enum Channel_regs |
paul@204 | 44 | { |
paul@204 | 45 | Dma_source = 0x00, // DSA |
paul@204 | 46 | Dma_destination = 0x04, // DTA |
paul@204 | 47 | Dma_transfer_count = 0x08, // DTC |
paul@204 | 48 | Dma_request_source = 0x0c, // DRT |
paul@204 | 49 | Dma_control_status = 0x10, // DCS |
paul@204 | 50 | Dma_command = 0x14, // DCM |
paul@204 | 51 | Dma_descriptor_address = 0x18, // DDA |
paul@204 | 52 | Dma_stride = 0x1c, // DSD |
paul@204 | 53 | }; |
paul@204 | 54 | |
paul@204 | 55 | enum Dma_control_bits : unsigned |
paul@204 | 56 | { |
paul@204 | 57 | Dma_fast_msc_transfer = 0x80000000, // FMSC |
paul@204 | 58 | Dma_fast_ssi_transfer = 0x40000000, // FSSI |
paul@204 | 59 | Dma_fast_tssi_transfer = 0x20000000, // FTSSI |
paul@204 | 60 | Dma_fast_uart_transfer = 0x10000000, // FUART |
paul@204 | 61 | Dma_fast_aic_transfer = 0x08000000, // FAIC |
paul@204 | 62 | Dma_control_trans_halted = 0x00000008, // HLT |
paul@204 | 63 | Dma_control_address_error = 0x00000004, // AR |
paul@204 | 64 | Dma_control_enable = 0x00000001, // DMAE |
paul@204 | 65 | }; |
paul@204 | 66 | |
paul@204 | 67 | enum Dma_transfer_count_bits : unsigned |
paul@204 | 68 | { |
paul@204 | 69 | Dma_transfer_count_mask = 0x00ffffff, |
paul@204 | 70 | }; |
paul@204 | 71 | |
paul@204 | 72 | enum Dma_request_source_bits : unsigned |
paul@204 | 73 | { |
paul@214 | 74 | Dma_request_type_mask = 0x0000003f, |
paul@204 | 75 | }; |
paul@204 | 76 | |
paul@204 | 77 | enum Dma_control_status_bits : unsigned |
paul@204 | 78 | { |
paul@204 | 79 | Dma_no_descriptor_transfer = 0x80000000, |
paul@204 | 80 | Dma_8word_descriptor = 0x40000000, |
paul@204 | 81 | Dma_copy_offset_mask = 0x0000ff00, |
paul@204 | 82 | Dma_address_error = 0x00000010, |
paul@204 | 83 | Dma_trans_completed = 0x00000008, |
paul@204 | 84 | Dma_trans_halted = 0x00000004, |
paul@204 | 85 | Dma_channel_enable = 0x00000001, |
paul@204 | 86 | |
paul@204 | 87 | Dma_copy_offset_shift = 8, |
paul@204 | 88 | }; |
paul@204 | 89 | |
paul@204 | 90 | enum Dma_command_bits : unsigned |
paul@204 | 91 | { |
paul@204 | 92 | Dma_source_address_increment = 0x800000, |
paul@204 | 93 | Dma_source_address_no_increment = 0x000000, |
paul@204 | 94 | Dma_destination_address_increment = 0x400000, |
paul@204 | 95 | Dma_destination_address_no_increment = 0x000000, |
paul@204 | 96 | |
paul@204 | 97 | Dma_source_address_increment_wrap = 0x200000, |
paul@204 | 98 | Dma_destination_address_increment_wrap = 0x100000, |
paul@204 | 99 | Dma_recommended_data_unit_size_mask = 0x0f0000, |
paul@204 | 100 | Dma_source_port_width_mask = 0x00c000, |
paul@204 | 101 | Dma_destination_port_width_mask = 0x003000, |
paul@204 | 102 | Dma_transfer_unit_size_mask = 0x000f00, |
paul@204 | 103 | |
paul@204 | 104 | Dma_trans_unit_size_32_bit = 0x000000, |
paul@204 | 105 | Dma_trans_unit_size_8_bit = 0x000100, |
paul@204 | 106 | Dma_trans_unit_size_16_bit = 0x000200, |
paul@204 | 107 | Dma_trans_unit_size_16_byte = 0x000300, |
paul@204 | 108 | Dma_trans_unit_size_32_byte = 0x000400, |
paul@204 | 109 | Dma_trans_unit_size_64_byte = 0x000500, |
paul@204 | 110 | Dma_trans_unit_size_128_byte = 0x000600, |
paul@204 | 111 | Dma_trans_unit_size_autonomous = 0x000700, |
paul@204 | 112 | Dma_trans_unit_size_external = 0x000800, |
paul@204 | 113 | |
paul@204 | 114 | Dma_source_address_compare_index = 0x000080, |
paul@204 | 115 | Dma_destination_address_compare_index = 0x000040, |
paul@204 | 116 | Dma_stride_enable = 0x000004, |
paul@204 | 117 | Dma_transfer_irq_enable = 0x000002, |
paul@204 | 118 | Dma_descriptor_link_enable = 0x000001, |
paul@204 | 119 | |
paul@204 | 120 | Dma_recommended_data_unit_size_shift = 16, |
paul@204 | 121 | Dma_source_port_width_shift = 14, |
paul@204 | 122 | Dma_destination_port_width_shift = 12, |
paul@204 | 123 | Dma_transfer_unit_size_shift = 8, |
paul@204 | 124 | }; |
paul@204 | 125 | |
paul@204 | 126 | enum Dma_port_width_values : unsigned |
paul@204 | 127 | { |
paul@204 | 128 | Dma_port_width_32_bit = 0, |
paul@204 | 129 | Dma_port_width_8_bit = 1, |
paul@204 | 130 | Dma_port_width_16_bit = 2, |
paul@204 | 131 | }; |
paul@204 | 132 | |
paul@204 | 133 | |
paul@204 | 134 | |
paul@204 | 135 | // Initialise a channel. |
paul@204 | 136 | |
paul@204 | 137 | Dma_x1600_channel::Dma_x1600_channel(Dma_x1600_chip *chip, uint8_t channel, |
paul@204 | 138 | l4_addr_t start, l4_cap_idx_t irq) |
paul@204 | 139 | : _chip(chip), _channel(channel), _irq(irq) |
paul@204 | 140 | { |
paul@204 | 141 | _regs = new Hw::Mmio_register_block<32>(start); |
paul@204 | 142 | |
paul@204 | 143 | // Initialise the transfer count. |
paul@204 | 144 | |
paul@204 | 145 | _regs[Dma_transfer_count] = 0; |
paul@204 | 146 | } |
paul@204 | 147 | |
paul@204 | 148 | // Return the closest interval length greater than or equal to the number of |
paul@204 | 149 | // units given encoded in the request detection interval length field of the |
paul@204 | 150 | // control/status register. |
paul@204 | 151 | |
paul@204 | 152 | uint32_t |
paul@204 | 153 | Dma_x1600_channel::encode_req_detect_int_length(uint8_t units) |
paul@204 | 154 | { |
paul@204 | 155 | static uint8_t lengths[] = {0, 1, 2, 3, 4, 8, 16, 32, 64, 128}; |
paul@204 | 156 | int i; |
paul@204 | 157 | |
paul@204 | 158 | if (!units) |
paul@204 | 159 | return 0; |
paul@204 | 160 | |
paul@204 | 161 | for (i = 0; i <= 9; i++) |
paul@204 | 162 | { |
paul@204 | 163 | if (lengths[i] >= units) |
paul@204 | 164 | break; |
paul@204 | 165 | } |
paul@204 | 166 | |
paul@204 | 167 | return i << Dma_recommended_data_unit_size_shift; |
paul@204 | 168 | } |
paul@204 | 169 | |
paul@204 | 170 | // Encode the appropriate source port width for the given request type. |
paul@204 | 171 | |
paul@204 | 172 | uint32_t |
paul@204 | 173 | Dma_x1600_channel::encode_source_port_width(uint8_t width) |
paul@204 | 174 | { |
paul@204 | 175 | switch (width) |
paul@204 | 176 | { |
paul@204 | 177 | case 1: |
paul@204 | 178 | return Dma_port_width_8_bit << Dma_source_port_width_shift; |
paul@204 | 179 | |
paul@204 | 180 | case 2: |
paul@204 | 181 | return Dma_port_width_16_bit << Dma_source_port_width_shift; |
paul@204 | 182 | |
paul@204 | 183 | default: |
paul@204 | 184 | return Dma_port_width_32_bit << Dma_source_port_width_shift; |
paul@204 | 185 | } |
paul@204 | 186 | } |
paul@204 | 187 | |
paul@204 | 188 | // Encode the appropriate destination port width for the given request type. |
paul@204 | 189 | |
paul@204 | 190 | uint32_t |
paul@204 | 191 | Dma_x1600_channel::encode_destination_port_width(uint8_t width) |
paul@204 | 192 | { |
paul@204 | 193 | switch (width) |
paul@204 | 194 | { |
paul@204 | 195 | case 1: |
paul@204 | 196 | return Dma_port_width_8_bit << Dma_destination_port_width_shift; |
paul@204 | 197 | |
paul@204 | 198 | case 2: |
paul@204 | 199 | return Dma_port_width_16_bit << Dma_destination_port_width_shift; |
paul@204 | 200 | |
paul@204 | 201 | default: |
paul@204 | 202 | return Dma_port_width_32_bit << Dma_destination_port_width_shift; |
paul@204 | 203 | } |
paul@204 | 204 | } |
paul@204 | 205 | |
paul@204 | 206 | // Encode the transfer unit size. |
paul@204 | 207 | // NOTE: This does not handle the external case. |
paul@204 | 208 | |
paul@204 | 209 | uint32_t |
paul@204 | 210 | Dma_x1600_channel::encode_transfer_unit_size(uint8_t size) |
paul@204 | 211 | { |
paul@204 | 212 | switch (size) |
paul@204 | 213 | { |
paul@204 | 214 | case 0: |
paul@204 | 215 | return Dma_trans_unit_size_autonomous; |
paul@204 | 216 | |
paul@204 | 217 | case 1: |
paul@204 | 218 | return Dma_trans_unit_size_8_bit; |
paul@204 | 219 | |
paul@204 | 220 | case 2: |
paul@204 | 221 | return Dma_trans_unit_size_16_bit; |
paul@204 | 222 | |
paul@204 | 223 | case 16: |
paul@204 | 224 | return Dma_trans_unit_size_16_byte; |
paul@204 | 225 | |
paul@204 | 226 | case 32: |
paul@204 | 227 | return Dma_trans_unit_size_32_byte; |
paul@204 | 228 | |
paul@204 | 229 | case 64: |
paul@204 | 230 | return Dma_trans_unit_size_64_byte; |
paul@204 | 231 | |
paul@204 | 232 | case 128: |
paul@204 | 233 | return Dma_trans_unit_size_128_byte; |
paul@204 | 234 | |
paul@204 | 235 | default: |
paul@204 | 236 | return Dma_trans_unit_size_32_bit; |
paul@204 | 237 | } |
paul@204 | 238 | } |
paul@204 | 239 | |
paul@256 | 240 | // Transfer data between memory locations, returning the number of units that |
paul@256 | 241 | // should have been transferred. |
paul@204 | 242 | |
paul@204 | 243 | unsigned int |
paul@204 | 244 | Dma_x1600_channel::transfer(uint32_t source, uint32_t destination, |
paul@204 | 245 | unsigned int count, |
paul@204 | 246 | bool source_increment, bool destination_increment, |
paul@204 | 247 | uint8_t source_width, uint8_t destination_width, |
paul@204 | 248 | uint8_t transfer_unit_size, |
paul@204 | 249 | enum Dma_x1600_request_type type) |
paul@204 | 250 | { |
paul@204 | 251 | printf("transfer:%s%s%s%s\n", error() ? " error" : "", |
paul@204 | 252 | halted() ? " halted" : "", |
paul@204 | 253 | completed() ? " completed" : "", |
paul@204 | 254 | _regs[Dma_transfer_count] ? " count" : ""); |
paul@204 | 255 | |
paul@204 | 256 | // Ensure an absence of address error and halt conditions globally and in this channel. |
paul@204 | 257 | |
paul@204 | 258 | if (error() || halted()) |
paul@204 | 259 | return 0; |
paul@204 | 260 | |
paul@260 | 261 | // Ensure a zero transfer count for this channel. |
paul@204 | 262 | |
paul@260 | 263 | if (_regs[Dma_transfer_count]) |
paul@204 | 264 | return 0; |
paul@204 | 265 | |
paul@204 | 266 | // Disable the channel. |
paul@204 | 267 | |
paul@204 | 268 | _regs[Dma_control_status] = _regs[Dma_control_status] & ~Dma_channel_enable; |
paul@204 | 269 | |
paul@204 | 270 | // Set addresses. |
paul@204 | 271 | |
paul@204 | 272 | _regs[Dma_source] = source; |
paul@204 | 273 | _regs[Dma_destination] = destination; |
paul@204 | 274 | |
paul@204 | 275 | // Set transfer count to the number of units. |
paul@204 | 276 | |
paul@204 | 277 | unsigned int units = count < Dma_transfer_count_mask ? count : Dma_transfer_count_mask; |
paul@204 | 278 | |
paul@204 | 279 | _regs[Dma_transfer_count] = units; |
paul@204 | 280 | |
paul@204 | 281 | // Set auto-request for memory-to-memory transfers. Otherwise, set the |
paul@204 | 282 | // indicated request type. |
paul@204 | 283 | |
paul@204 | 284 | _regs[Dma_request_source] = type; |
paul@204 | 285 | |
paul@204 | 286 | // For a descriptor, the actual fields would be populated instead of the |
paul@204 | 287 | // command register, descriptor transfer would be indicated in the control/ |
paul@204 | 288 | // status register along with the appropriate descriptor size indicator. |
paul@204 | 289 | |
paul@204 | 290 | /* NOTE: To be considered... |
paul@204 | 291 | * request detection interval length (for autonomous mode) |
paul@204 | 292 | */ |
paul@204 | 293 | |
paul@204 | 294 | _regs[Dma_command] = (source_increment ? Dma_source_address_increment : Dma_source_address_no_increment) | |
paul@204 | 295 | (destination_increment ? Dma_destination_address_increment : Dma_destination_address_no_increment) | |
paul@204 | 296 | encode_source_port_width(source_width) | |
paul@204 | 297 | encode_destination_port_width(destination_width) | |
paul@204 | 298 | encode_transfer_unit_size(transfer_unit_size) | |
paul@204 | 299 | Dma_transfer_irq_enable; |
paul@204 | 300 | |
paul@204 | 301 | // For a descriptor, the descriptor address would be set and the doorbell |
paul@204 | 302 | // register field for the channel set. |
paul@204 | 303 | |
paul@204 | 304 | // Enable the channel (and peripheral). |
paul@204 | 305 | |
paul@204 | 306 | _regs[Dma_control_status] = Dma_no_descriptor_transfer | |
paul@204 | 307 | Dma_channel_enable; |
paul@204 | 308 | |
paul@204 | 309 | // Return the number of units to transfer. |
paul@204 | 310 | |
paul@204 | 311 | return units; |
paul@204 | 312 | } |
paul@204 | 313 | |
paul@256 | 314 | // Wait for a transfer to end, returning the number of units remaining to be |
paul@256 | 315 | // transferred. |
paul@256 | 316 | |
paul@204 | 317 | unsigned int |
paul@204 | 318 | Dma_x1600_channel::wait() |
paul@204 | 319 | { |
paul@204 | 320 | // An interrupt will occur upon completion, the completion flag will be set |
paul@204 | 321 | // and the transfer count will be zero. |
paul@204 | 322 | |
paul@204 | 323 | unsigned int remaining = 0; |
paul@204 | 324 | |
paul@204 | 325 | do |
paul@204 | 326 | { |
paul@204 | 327 | if (!wait_for_irq(1000000)) |
paul@204 | 328 | printf("status = %x\n", (uint32_t) _regs[Dma_control_status]); |
paul@204 | 329 | else |
paul@204 | 330 | { |
paul@204 | 331 | printf("status = %x\n", (uint32_t) _regs[Dma_control_status]); |
paul@204 | 332 | remaining = _regs[Dma_transfer_count]; |
paul@204 | 333 | ack_irq(); |
paul@204 | 334 | break; |
paul@204 | 335 | } |
paul@204 | 336 | } |
paul@204 | 337 | while (!error() && !halted() && !completed()); |
paul@204 | 338 | |
paul@204 | 339 | // Reset the channel status. |
paul@204 | 340 | |
paul@204 | 341 | _regs[Dma_control_status] = _regs[Dma_control_status] & ~(Dma_channel_enable | |
paul@204 | 342 | Dma_trans_completed | Dma_address_error | |
paul@204 | 343 | Dma_trans_halted); |
paul@204 | 344 | _regs[Dma_transfer_count] = 0; |
paul@204 | 345 | |
paul@204 | 346 | return remaining; |
paul@204 | 347 | } |
paul@204 | 348 | |
paul@204 | 349 | // Wait indefinitely for an interrupt request, returning true if one was delivered. |
paul@204 | 350 | |
paul@204 | 351 | bool |
paul@204 | 352 | Dma_x1600_channel::wait_for_irq() |
paul@204 | 353 | { |
paul@268 | 354 | if (l4_error(l4_rcv_ep_bind_thread(_irq, pthread_l4_cap(pthread_self()), 0))) |
paul@268 | 355 | return false; |
paul@268 | 356 | |
paul@204 | 357 | return !l4_error(l4_irq_receive(_irq, L4_IPC_NEVER)) && _chip->have_interrupt(_channel); |
paul@204 | 358 | } |
paul@204 | 359 | |
paul@204 | 360 | // Wait up to the given timeout (in microseconds) for an interrupt request, |
paul@204 | 361 | // returning true if one was delivered. |
paul@204 | 362 | |
paul@204 | 363 | bool |
paul@204 | 364 | Dma_x1600_channel::wait_for_irq(unsigned int timeout) |
paul@204 | 365 | { |
paul@268 | 366 | if (l4_error(l4_rcv_ep_bind_thread(_irq, pthread_l4_cap(pthread_self()), 0))) |
paul@268 | 367 | return false; |
paul@268 | 368 | |
paul@204 | 369 | return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, l4util_micros2l4to(timeout)))) && _chip->have_interrupt(_channel); |
paul@204 | 370 | } |
paul@204 | 371 | |
paul@204 | 372 | // Acknowledge an interrupt condition. |
paul@204 | 373 | |
paul@204 | 374 | void |
paul@204 | 375 | Dma_x1600_channel::ack_irq() |
paul@204 | 376 | { |
paul@204 | 377 | _chip->ack_irq(_channel); |
paul@204 | 378 | } |
paul@204 | 379 | |
paul@204 | 380 | // Return whether a transfer has completed. |
paul@204 | 381 | |
paul@204 | 382 | bool |
paul@204 | 383 | Dma_x1600_channel::completed() |
paul@204 | 384 | { |
paul@204 | 385 | return _regs[Dma_control_status] & Dma_trans_completed ? true : false; |
paul@204 | 386 | } |
paul@204 | 387 | |
paul@204 | 388 | // Return whether an address error condition has arisen. |
paul@204 | 389 | |
paul@204 | 390 | bool |
paul@204 | 391 | Dma_x1600_channel::error() |
paul@204 | 392 | { |
paul@204 | 393 | return _chip->error() || (_regs[Dma_control_status] & Dma_address_error ? true : false); |
paul@204 | 394 | } |
paul@204 | 395 | |
paul@204 | 396 | // Return whether a transfer has halted. |
paul@204 | 397 | |
paul@204 | 398 | bool |
paul@204 | 399 | Dma_x1600_channel::halted() |
paul@204 | 400 | { |
paul@204 | 401 | return _chip->halted() || (_regs[Dma_control_status] & Dma_trans_halted ? true : false); |
paul@204 | 402 | } |
paul@204 | 403 | |
paul@204 | 404 | |
paul@204 | 405 | |
paul@204 | 406 | // Initialise the I2C controller. |
paul@204 | 407 | |
paul@204 | 408 | Dma_x1600_chip::Dma_x1600_chip(l4_addr_t start, l4_addr_t end, |
paul@204 | 409 | Cpm_x1600_chip *cpm) |
paul@204 | 410 | : _start(start), _end(end), _cpm(cpm) |
paul@204 | 411 | { |
paul@204 | 412 | _regs = new Hw::Mmio_register_block<32>(start); |
paul@204 | 413 | } |
paul@204 | 414 | |
paul@204 | 415 | // Enable the peripheral. |
paul@204 | 416 | |
paul@204 | 417 | void |
paul@204 | 418 | Dma_x1600_chip::enable() |
paul@204 | 419 | { |
paul@204 | 420 | // Make sure that the DMA clock is available. |
paul@204 | 421 | |
paul@204 | 422 | _cpm->start_clock(Clock_dma); |
paul@204 | 423 | |
paul@204 | 424 | _regs[Dma_control] = Dma_control_enable; |
paul@204 | 425 | while (!(_regs[Dma_control] & Dma_control_enable)); |
paul@204 | 426 | } |
paul@204 | 427 | |
paul@204 | 428 | // Disable the channel. |
paul@204 | 429 | |
paul@204 | 430 | void |
paul@204 | 431 | Dma_x1600_chip::disable() |
paul@204 | 432 | { |
paul@204 | 433 | _regs[Dma_control] = 0; |
paul@204 | 434 | while (_regs[Dma_control] & Dma_control_enable); |
paul@204 | 435 | } |
paul@204 | 436 | |
paul@204 | 437 | // Obtain a channel object. |
paul@204 | 438 | |
paul@204 | 439 | Dma_x1600_channel * |
paul@204 | 440 | Dma_x1600_chip::get_channel(uint8_t channel, l4_cap_idx_t irq) |
paul@204 | 441 | { |
paul@204 | 442 | if (channel < 32) |
paul@204 | 443 | return new Dma_x1600_channel(this, channel, _start + 0x20 * channel, irq); |
paul@204 | 444 | else |
paul@204 | 445 | throw -L4_EINVAL; |
paul@204 | 446 | } |
paul@204 | 447 | |
paul@204 | 448 | // Return whether an interrupt is pending on the given channel. |
paul@204 | 449 | |
paul@204 | 450 | bool |
paul@204 | 451 | Dma_x1600_chip::have_interrupt(uint8_t channel) |
paul@204 | 452 | { |
paul@251 | 453 | return _regs[Dma_irq_pending] & (1UL << channel) ? true : false; |
paul@204 | 454 | } |
paul@204 | 455 | |
paul@204 | 456 | // Acknowledge an interrupt condition on the given channel. |
paul@204 | 457 | |
paul@204 | 458 | void |
paul@204 | 459 | Dma_x1600_chip::ack_irq(uint8_t channel) |
paul@204 | 460 | { |
paul@251 | 461 | _regs[Dma_irq_pending] = _regs[Dma_irq_pending] & ~(1UL << channel); |
paul@204 | 462 | } |
paul@204 | 463 | |
paul@204 | 464 | // Return whether an address error condition has arisen. |
paul@204 | 465 | |
paul@204 | 466 | bool |
paul@204 | 467 | Dma_x1600_chip::error() |
paul@204 | 468 | { |
paul@204 | 469 | return _regs[Dma_control] & Dma_control_address_error ? true : false; |
paul@204 | 470 | } |
paul@204 | 471 | |
paul@204 | 472 | // Return whether a transfer has halted. |
paul@204 | 473 | |
paul@204 | 474 | bool |
paul@204 | 475 | Dma_x1600_chip::halted() |
paul@204 | 476 | { |
paul@204 | 477 | return _regs[Dma_control] & Dma_control_trans_halted ? true : false; |
paul@204 | 478 | } |
paul@204 | 479 | |
paul@204 | 480 | |
paul@204 | 481 | |
paul@204 | 482 | // C language interface functions. |
paul@204 | 483 | |
paul@204 | 484 | void *x1600_dma_init(l4_addr_t start, l4_addr_t end, void *cpm) |
paul@204 | 485 | { |
paul@204 | 486 | return (void *) new Dma_x1600_chip(start, end, static_cast<Cpm_x1600_chip *>(cpm)); |
paul@204 | 487 | } |
paul@204 | 488 | |
paul@204 | 489 | void x1600_dma_disable(void *dma_chip) |
paul@204 | 490 | { |
paul@204 | 491 | static_cast<Dma_x1600_chip *>(dma_chip)->disable(); |
paul@204 | 492 | } |
paul@204 | 493 | |
paul@204 | 494 | void x1600_dma_enable(void *dma_chip) |
paul@204 | 495 | { |
paul@204 | 496 | static_cast<Dma_x1600_chip *>(dma_chip)->enable(); |
paul@204 | 497 | } |
paul@204 | 498 | |
paul@204 | 499 | void *x1600_dma_get_channel(void *dma, uint8_t channel, l4_cap_idx_t irq) |
paul@204 | 500 | { |
paul@204 | 501 | return static_cast<Dma_x1600_chip *>(dma)->get_channel(channel, irq); |
paul@204 | 502 | } |
paul@204 | 503 | |
paul@204 | 504 | unsigned int x1600_dma_transfer(void *dma_channel, |
paul@204 | 505 | uint32_t source, uint32_t destination, |
paul@204 | 506 | unsigned int count, |
paul@204 | 507 | int source_increment, int destination_increment, |
paul@204 | 508 | uint8_t source_width, uint8_t destination_width, |
paul@204 | 509 | uint8_t transfer_unit_size, |
paul@204 | 510 | enum Dma_x1600_request_type type) |
paul@204 | 511 | { |
paul@204 | 512 | return static_cast<Dma_x1600_channel *>(dma_channel)->transfer(source, |
paul@204 | 513 | destination, count, source_increment, destination_increment, source_width, |
paul@204 | 514 | destination_width, transfer_unit_size, type); |
paul@204 | 515 | } |
paul@204 | 516 | |
paul@204 | 517 | unsigned int x1600_dma_wait(void *dma_channel) |
paul@204 | 518 | { |
paul@204 | 519 | return static_cast<Dma_x1600_channel *>(dma_channel)->wait(); |
paul@204 | 520 | } |